5

9/27/00

SPT5510

Wideband decoupling is required for optimum settling per-

formance. This may require several capacitors in parallel,

and series resistors when appropriate, to reduce resonance

effects. Some applications may need only a single capaci-

tor; however, decoupling influences both long- and short-

term settling, so caution is urged. Your application may

require some research to determine the optimum power

supply decoupling network.

DIGITAL INPUTS AND TIMING

Each digital input is buffered, decoded, and then latched

into D flip-flops which drive the output switches. Master-

slave flip-flops are not used; thus, there is only a 1/2 clock

period delay (max) from data change to output change. In

this architecture, clock and data edge speeds (i.e., rise/fall

times) may affect data feedthrough. Using a data edge of

approximately 0.8 ns will cause data feedthrough of about

10 pV-s, while a 5 ns data edge will reduce the feedthrough

to about 4 pV-s. Data lines may include series resistors or

RC filters for edge control if desired.

The clock signal controls when the data is latched into the

flip-flops. When the CLK is high, the DAC is in track mode. A

negative going CLK latches the data. If CLK is held low, the

DAC is in hold mode. See figure 2.

OUTPUTS

The output is comprised of current sinks, R-2R ladder, and

associated parasitics. See figure 3 for an equivalent output

circuit.

The DAC’s full-scale output current when using the internal

reference amplifier is determined by the voltage at pin

an LSB) by using the following formula:

The inputs determine whether the current from each sink

Code (D15 is MSB)

0 (zero scale)

No current

All current

32768 (mid-scale)

65535 (full-scale)

All current

No current

Differential outputs facilitate maximum noise rejection and

signal swing. The DAC is trimmed using a current to voltage

(I-V) converter which provides a virtual ground at the out-

puts and includes sense lines to mitigate the impact of bus

drops. Operating into a load other than a virtual ground will

introduce a slight bow at the output. This bow is related to

the current sinks’ finite output impedance and ladder

impedance.

An example circuit using an I-V converter is shown in figure

4. Note that resistor and op-amp self heating over the DAC’s

full-scale range will introduce additional temperature depen-

dence. The op-amp and feedback resistor must both have

very low tempcos if the DAC’s intrinsic gain drift is to be

maintained. A sense line helps reduce wire effects – both IR

loss and temperature drift.

Figure 2 – Timing Diagram

CLK

DATA

Figure 3 – Equivalent Output Circuit

10 pF

1.1k

+

–

OGND

OGND

OGND

OGND

GND

GND

250

250

BNC

BNC

Figure 4 – I-V Converter