CS5521 datasheet(29/56 Pages) CIRRUS

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CS5521/22/23/24/28

DS317F8

sume 9.0 mW. The CS5521/23 typically consume

6.0 mW. The low-power mode is an alternate mode

in the CS5522/24/28 that reduces the consumed

power to 5.5 mW. It is entered by setting bit D8

(the low-power mode bit) in the configuration reg-

ister to logic 1. Slightly degraded noise or linearity

performance should be expected in the low-power

mode. Note that the XIN clock should not exceed

130 kHz in low-power mode. The final two modes

accommodated in all devices are referred to as the

power save modes. They power down most of the

analog portion of the chip and stop filter convolu-

tions. The power-save modes are entered whenever

the PS/R bit of the configuration register is set to

logic 1. The particular power-save mode entered

depends on state of bit D11 (PSS, the Power Save

Select bit) in the configuration register. If PSS is

logic 0, the converters enters the standby mode re-

ducing the power consumption to 1.2 mW. If the

PSS bit (bit D11) is set to logic zero, the PD bit (bit

D10) must be set to one. The standby mode leaves

the oscillator and the on-chip bias generator run-

ning. This allows the converter to quickly return to

the normal or low-power mode once the PS/R bit is

set back to a logic 0. If PSS and PS/R in the config-

uration register are set to logic 1, the sleep mode is

entered reducing the consumed power to around

500

μW. Since the sleep mode disables the oscilla-

tor, a 500 ms oscillator start-up delay period is re-

quired before returning to the normal or low-power

mode.

1.2.7.4 Charge Pump Disable

The pump disable (PD) bit permits the user to turn

off the charge pump drive thus enabling the user to

reduce the radiation of digital interference from the

CPD pin when the charge pump is not being used.

1.2.7.5 Reset System Control Bits

The reset system (RS) bit permits the user to per-

form a system reset. A system reset can be initiated

at any time by writing a logic 1 to the RS bit in the

configuration register. After a system reset cycle is

complete, the reset valid (RV) bit is set indicating

that the internal logic was properly reset. The RV

remains set until the configuration register is read.

Note that the user must write a logic 0 to the RS bit

to take the part out of the reset mode. No other bits

in the configuration register can be written at this

time. A subsequent write to the configuration reg-

ister is necessary to write to any other bits in this

tialized to the following states.

1.2.7.6 Data Conversion Error Flags

The oscillation detect (OD) and overflow (OF) bits

in the configuration register are flag bits used to in-

dicate that the ADC performed a conversion on an

input signal that was not within the conversion

range of the ADC. For convenience, the OD and

OF bits are also in the data conversion word of the

CS5521/23.

The OF bit is set to logic 1 when the input signal is:

1) more positive than full scale

2) more negative than zero in unipolar mode, or

3) more negative than negative full scale in bipo-

lar mode.

The OF flag is cleared to logic 0 when a conversion

occurs which is not out of range.

The OD bit is set to logic 1 any time that an oscil-

latory condition is detected in the modulator. This

does not occur under normal operating conditions,

but may occur when the input is extremely over-

ranged. The OD flag will be cleared to logic 0 when

the modulator becomes stable.

configuration register:

000040(H)

offset registers:

000000(H)

gain registers:

400000(H)

channel setup registers:

000000(H)

CS5521 数据表(PDF) 29 Page - Cirrus Logic

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