CS5521 datasheet(30/56 Pages) CIRRUS

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CS5521/22/23/24/28

DS317F8

D23(MSB)

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

CFS1

CFS0

DP3

DP2

DP1

DP0

D11

D10

PSS

PS/R

LPM

BIT

NAME

VALUE

FUNCTION

D23-D22

Not Used, NU

1.R indicates the bit value after the part is reset.

Must always be logic 0.

D21-D20

Chop Frequency Select,

CFS1-CFS0

R 256 Hz Amplifier chop frequency.

(XIN = 32.768 kHz)

4,096 Hz Amplifier chop frequency.

16,384 Hz Amplifier chop frequency.

1,024 Hz Amplifier chop frequency.

D19

Not Used, NU

R Must always be logic 0.

D18

Multiple Conversion, MC

R Perform single-Setup conversions. MC bit is ignored during calibrations.

Perform multiple-Setup conversions on Setups in the channel-setup reg-

ister by issuing only one command with MSB = 1.

D17

Loop, LP

R The conversions on the single Setup (MC = 0) or multiple Setups (MC =

1) are performed only once.

The conversions on the single Setup (MC = 0) or multiple Setups (MC =

1) are continuously performed.

D16

Read Convert, RC

R Don’t wait for user to finish reading data before starting new conversions.

The RC bit is used in conjunction with the LP bit when the LP bit is set to

logic 1. If LP = 0, the RC bit is ignored. If LP = 1, the ADC waits for user to

read data conversion(s) before converting again. The RC bit is ignored

during calibrations. Refer to Calibration Protocol for details.

D15-D12

Depth Pointer, DP3-DP0

0000

1111

R When writing or reading the CSRs, these bits (DP3-DP0) determine the

number of CSR’s to be accessed (0000=1). They are also used to deter-

mine how many Setups are converted when MC=1 and a command byte

with its MSB = 1 is issued. Note that the CS5522 has two CSRS, the

CS5524 has four CSRs, and the CS5528 has 8 CSRs.

D11

Power Save Select, PSS

2.When the chip is placed in standby mode, the PD bit (bit D10) should be set to 1.

R Standby Mode (Oscillator active, allows quick power-up).

Sleep Mode (Oscillator inactive).

D10

Pump Disable, PD

R Charge Pump Enabled.

For PD = 1, the CPD pin goes to a Hi-Z output state.

Power Save/Run, PS/R

R Run.

Power Save.

Low Power Mode, LPM

R Normal Mode (LPM bit is only for the CS5522/24/28)

Reduced Power Mode

Reset System, RS

R Normal Operation.

Activate a Reset cycle. To return to Normal Operation write bit to zero.

Reset Valid, RV

No reset has occurred or bit has been cleared (read only).

Bit is set after a Valid Reset has occurred. (Cleared when read.)

Oscillation Detect, OD

R Bit is clear when an oscillation condition has not occurred (read only).

Bit is set when an oscillatory condition is detected in the modulator.

Overrange Flag, OF

R Bit is clear when an overrange condition has not occurred (read only).

Bit is set when input signal is more positive than the positive full scale,

more negative than zero (unipolar mode), or when the input is more neg-

ative than the negative full scale (bipolar mode).

D3-D0

Not Used, NU

0000

R Must always be logic 0.

Table 4. Configuration Register

CS5521 数据表(PDF) 30 Page - Cirrus Logic

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CS5521 数据表(PDF) 30 Page - Cirrus Logic

CS5521 数据表(HTML) 30 Page - Cirrus Logic

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