CS5521 datasheet(39/56 Pages) CIRRUS

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CS5521/22/23/24/28

DS317F8

SD0. After ‘1111 1111’ is provided, 24 additional

SCLKs are required to transfer the last 3 bytes of

conversion data before the serial port will return to

the command mode.

Example 3:

The configuration register has the following bits as

shown:

DP3-DP = ‘0101’,

MC = 1,

LP = 0,

RC = X. The command issued is ‘1XXX X000’.

These settings instruct the converter to perform a

single conversion on six Setups once. The order in

which the channels are converted is 6, 1, 6, 2, 6, and

3. SDO falls after physical channel 3 is converted.

To read the 6 conversion results 8 SCLKs are re-

quired to clear the SD0 flag. Then 144 additional

SCLKs are required to read the conversion data

from the FIFO. Again, the order in which the data

is provided is the same as the order in which the

channels are converted. After the last 3 bytes of the

conversion data corresponding to physical channel

3 is read, the serial port automatically returns to the

command mode where it will remain until the next

valid command byte is received.

Example 4:

The configuration register has the following bits as

shown:

DP3-DP0 = ‘1001’,

MC = 1,

LP = 1,

RC = 0.

The

command

byte

issued

‘1XXX X000’. These settings instruct the convert-

er to repeatedly perform multiple-setup conver-

sions using ten Setups. The order in which the

channels are converted is: 6, 1, 6, 2, 6, 3, 6, 4, 6, 5.

SDO falls after physical channel 5 is converted. To

read the 10 conversion results 8 SCLKs with

SDI = 0 are required to clear the SD0 flag. Then

240 more SCLKs are required to read the conver-

sion data from the FIFO. The order in which the

data is provided is the same as the order in which

the channels are converted. The first 3 bytes of data

correspond to the first Setup which in this example

is physical channel 6; the next 3 bytes of data cor-

respond to the second Setup which in this example

is physical channel 1; and, the last 3 bytes of data

corresponds to 10th Setup which here is physical

channel 5. Since the Setups are converted in the

background, while the data is being read, the user

must finish reading the conversion data FIFO be-

fore it is updated with new conversions. To exit this

conversion

mode

the

user

must

provide

‘1111 1111’ to SDI during the first 8 SCLKs. If a

byte of 1’s is provided, the serial port returns to the

command mode only after the conversion data

FIFO is emptied (in this case 10 conversions are

performed). Note that in this example physical

channel 6 is converted five times. Each conversion

could be with the same or different filter rates de-

pending on the setting of Setups 1, 3, 5, 7 and 9.

Note that there is only one offset and one gain reg-

ister per physical channel. Therefore, any physical

channel can only be calibrated for the gain range

selected during calibration. Specifying a different

gain range in the Setup other than the range that

was calibrated will result in a gain error.

Example 5:

The configuration register has the following bits as

shown: DP3-DP0 = ‘XXXX’, MC = X, LP = X,

RC = X. The command issued is ‘1010 1101’.

These settings instruct the converter to perform a

system offset calibration of the 6th Setup (which is

physical channel 3 in this example). During cali-

bration, the serial port remains in the command

mode. Once the calibration is completed, SDO

falls. To perform additional calibrations, more

commands have to be issued.

Notes: 1)The configuration register must be written before

channel-setup registers (CSRs) because the depth

information contained in the configuration regis-

ter defines how many of the CSRs to use.

2) The CSRs need to be written regardless of single

conversion or multiple single conversion mode.

3) When single-Setup conversions (MC = 0) are de-

sired, the channel address is embedded in the

command byte. In the multiple-Setup conversion

mode (MC = 1), channels are selected in a pre-

programmed order based on information con-

tained in the CSRs and the depth bits (DP3-DP0)

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