CS8422 datasheet(39/82 Pages) CIRRUS

39 / 82 page

DS692PP2

CS8422

7.4.1

Hardware Mode Control

In Hardware Mode, the default master clock source for the SRC is the internal ring oscillator. Therefore,

it is not necessary to apply an external MCLK source for the SRC. Optionally the user may select the PLL

clock as the SRC MCLK source by connecting a 20 k

Ω pull-up resistor between MCLK_OUT and VL.

7.4.2

Software Mode Control

In Software Mode, the SRC master clock source is selected by the SRC_MCLK[1:0] bits in the “SRC Out-

put Serial Port Clock Control (08h)” register. If the XTI clock is selected as the SRC MCLK and XTI is tied

to VL or DGND and XTO is left unconnected, then the internal ring oscillator will take the place of the XTI-

XTO clock source.

If the selected SRC MCLK source is XTI-XTO, and is greater that 33 MHz, the user can enable the internal

clock divide-by-two by setting the SRC_DIV bit in control port register 08h. See “SRC Output Serial Port

Clock Control (08h)” on page 51 for more details.

8. HARDWARE MODE CONTROL

The CS8422 provides a stand-alone hardware control mode in which the part does not require an I²C or SPI control

port. In Hardware Mode, the user is provided with a subset of the features available in Software Mode as shown in

Figure 21. The part will be in Hardware Mode if there is a 20 k

Ω pull-up resistor connected between the C pin and

VL upon reset.

Controlling the CS8422 in Hardware Mode is done through dedicated control inputs, 20 k

Ω pull-up or pull-down re-

sistors attached to dual-purpose pins, and by attaching a specific resistor values from one of two dedicated control

pins (SAOF and MS_SEL) to either VL or ground. In the case of SAOF and MS_SEL, the resistor should be con-

nected as close to the pin as possible and should have a tolerance no greater than ±1%. Dedicated controls

(TX_SEL and RX_SEL) can be changed during operation whereas pull-up resistor controls are sensed on startup.

Figure 21 shows clock routing options available in Hardware Mode. Control signal names are in italics and are de-

scribed in the table below.

RXP/RXN0

RXP/RXN1

Receiver

Clock

Recovery

(PLL)

Sam ple

Rate

Converter

Serial

Audio

Output

OLR CK1

OSCLK1

SDOU T1

TDM _IN1

OLR CK2

OSCLK2

SDOU T2

Serial

Audio

Output

RX_SEL

TX_SEL

Ring O scillator

(RMCK Pull-Up)

2:1

MUX

(M C LK_O U T Pull-up)

Clock

Generator

XTI XTO

MCLK_O UT

2:1

MUX

2:1

MUX

MS_SEL

SAOF

M S_SEL

SA OF

RM CK

2:1

MUX

Figure 21. Hardware Mode Clock Routing

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