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CS8422 数据表(PDF) 45 Page - Cirrus Logic

部件名 CS8422
功能描述  24-bit, 192-kHz, Asynchronous Sample Rate Converter with Integrated Digital Audio Interface Receiver
PDF  82 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS8422 数据表(HTML) 45 Page - Cirrus Logic

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background image
DS692PP2
45
CS8422
11h
Receiver Chan-
nel
Status
AUX3
AUX2
AUX1
AUX0
PRO
COPY
ORIG
EMPH
12h
Format Detect
Status
PCM
IEC61937
DTS_LD
DTS_CD
HD_CD
DGTL_SIL
Reserved
Reserved
13h
Receiver Error
ACTIVE
QCRC
CCRC
UNLOCK
V
CONF
BIP
PAR
14h
Interrupt
Status
PCCH
OSLIP
DETC
CCH
RERR
QCH
FCH
SRC_
UNLOCK
15h
PLL Status
RX_
ACTIVE
ISCLK_
ACTIVE
PLL_LOCK
96KHZ
192KHZ
Reserved
Reserved
Reserved
16h
Receiver
Status
CS_
UPDATE
RCVR_
RATE1
RCVR_
RATE0
RX_LOCK
BLK_VERR
BLK_CERR
BLK_BERR
BLK_PERR
0
17h
Fs/XTI Ratio
1
FS_XT15
FS_XT14
FS_XT13
FS_XT12
FS_XT11
FS_XT10
FS_XT9
FS_XT8
18h
Fs/XTI Ratio
2
FS_XT7
FS_XT6
FS_XT5
FS_XT4
FS_XT3
FS_XT2
FS_XT1
FS_XT0
19h
Q Subcode 1
CONTROL
CONTROL
CONTROL
CONTROL
ADDRESS
ADDRESS
ADDRESS
ADDRESS
1Ah
Q Subcode 2
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
TRACK
1Bh
Q Subcode 3
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
INDEX
1Ch
Q Subcode 4
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
MINUTE
1Dh
Q Subcode 5
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
SECOND
1Eh
Q Subcode 6
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
FRAME
1Fh
Q Subcode 7
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
ZERO
20h
Q Subcode 8
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
ABS
MINUTE
21h
Q Subcode 9
ABS
SECOND
ABS
SECOND
ABS
SECOND
ABS
SECOND
ABS
SECOND
ABS
SECOND
ABS
SECOND
ABS
SECOND
22h
Q Subcode 10
ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME
23h
Channel A Sta-
tus Byte 0
AC0[7]
AC0[6]
AC0[5]
AC0[4]
AC0[3]
AC0[2]
AC0[1]
AC0[0]
24h
Channel A Sta-
tus Byte 1
AC1[7]
AC1[6]
AC1[5]
AC1[4]
AC1[3]
AC1[2]
AC1[1]
AC1[0]
25h
Channel A Sta-
tus Byte 2
AC2[7]
AC2[6]
AC2[5]
AC2[4]
AC2[3]
AC2[2]
AC2[1]
AC2[0]
26h
Channel A Sta-
tus Byte 3
AC3[7]
AC3[6]
AC3[5]
AC3[4]
AC3[3]
AC3[2]
AC3[1]
AC3[0]
27h
Channel A Sta-
tus Byte 4
AC4[7]
AC4[6]
AC4[5]
AC4[4]
AC4[3]
AC4[2]
AC4[1]
AC4[0]
28h
Channel B Sta-
tus Byte 0
BC0[7]
BC0[6]
BC0[5]
BC0[4]
BC0[3]
BC0[2]
BC0[1]
BC0[0]
29h
Channel B Sta-
tus Byte 1
BC1[7]
BC1[6]
BC1[5]
BC1[4]
BC1[3]
BC1[2]
BC1[1]
BC1[0]
2Ah
Channel B Sta-
tus Byte 2
BC2[7]
BC2[6]
BC2[5]
BC2[4]
BC2[3]
BC2[2]
BC2[1]
BC2[0]
2Bh
Channel B Sta-
tus Byte 3
BC3[7]
BC3[6]
BC3[5]
BC3[4]
BC3[3]
BC3[2]
BC3[1]
BC3[0]
Addr
Function
7
6
5
4
3
2
1
0
Table 6. Summary of Software Register Bits (Continued)



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