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AD8155ACPZ-R7 数据表(PDF) 28 Page - Analog Devices

部件名 AD8155ACPZ-R7
功能描述  6.5 Gbps Dual Buffer Mux/Demux
PDF  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD8155ACPZ-R7 数据表(HTML) 28 Page - Analog Devices

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AD8155
Rev. 0 | Page 28 of 36
SIGNAL LEVELS AND COMMON-MODE SHIFT FOR AC-COUPLED AND DC-COUPLED OUTPUTS
Table 19. Output Voltage Range and Output Common-Mode Shift vs. Output Level and PE Setting
Output Levels and PE Boost
Register
Setting
Output
Current
AC-Coupled Transmitter
DC-Coupled Transmitter
VCC = VTTO = 3.3 V VCC = VTTO = 1.8 V
VCC = VTTO = 3.3 V VCC = VTTO = 1.8 V
VSW-DC1
(mV)
VSW-PE1
(mV)
PE
Boost
(%)
PE (dB)
TX[A/B/C]
Level/PE
Control2
ITTO1 (mA)
ΔVOCM1
(mV)
VH-PE1
(V)
VL-PE1
(V)
VH-PE1
(V)
VL-PE1
(V)
ΔVOCM1
(mV)
VH-PE1
(V)
VL-PE1
(V)
VH-PE1
(V)
VL-PE1
(V)
200
200
0.00
0.00
0x00
8
200
3.2
3
1.7
1.5
100
3.3
3.1
1.8
1.6
200
300
50.00
3.52
0x01
12
300
3.15
2.85
1.65
1.35
150
3.3
3
1.8
1.5
200
400
100.00
6.02
0x02
16
400
3.1
2.7
1.6
1.2
200
3.3
2.9
1.8
1.4
200
500
150.00
7.96
0x03
20
500
3.05
2.55
1.55
1.05
250
3.3
2.8
1.8
1.3
200
600
200.00
9.54
0x04
24
600
3
2.4
1.5
0.9
300
3.3
2.7
1.8
1.2
200
700
250.00
10.88
0x05
28
700
2.95
2.25
1.45
0.75
350
3.3
2.6
1.8
1.1
200
800
300.00
12.04
0x06
32
800
2.9
2.1
1.4
0.6
400
3.3
2.5
1.8
1
300
300
0.00
0.00
0x10
12
300
3.15
2.85
1.65
1.35
150
3.3
3
1.8
1.5
300
400
33.33
2.50
0x11
16
400
3.1
2.7
1.6
1.2
200
3.3
2.9
1.8
1.4
300
500
66.67
4.44
0x12
20
500
3.05
2.55
1.55
1.05
250
3.3
2.8
1.8
1.3
300
600
100.00
6.02
0x13
24
600
3
2.4
1.5
0.9
300
3.3
2.7
1.8
1.2
300
700
133.33
7.36
0x14
28
700
2.95
2.25
1.45
0.75
350
3.3
2.6
1.8
1.1
300
800
166.67
8.52
0x15
32
800
2.9
2.1
1.4
0.6
400
3.3
2.5
1.8
1
300
900
200.00
9.54
0x16
36
900
2.85
1.95
1.35
0.45
450
3.3
2.4
1.8
0.9
400
400
0.00
0.00
0x20
16
400
3.1
2.7
1.6
1.2
200
3.3
2.9
1.8
1.4
400
500
25.00
1.94
0x21
20
500
3.05
2.55
1.55
1.05
250
3.3
2.8
1.8
1.3
400
600
50.00
3.52
0x22
24
600
3
2.4
1.5
0.9
300
3.3
2.7
1.8
1.2
400
700
75.00
4.86
0x23
28
700
2.95
2.25
1.45
0.75
350
3.3
2.6
1.8
1.1
400
800
100.00
6.02
0x24
32
800
2.9
2.13
1.4
0.6
400
3.3
2.5
1.8
1
400
900
125.00
7.04
0x25
36
900
2.85
1.954
1.35
0.45
450
3.3
2.4
1.8
0.9
400
1000
150.00
7.96
0x26
40
1000
2.8
1.84
1.3
0.3
500
3.3
2.3
1.8
0.8
600
600
0.00
0.00
0x30
24
600
3
2.4
1.5
0.9
300
3.3
2.7
1.8
1.2
600
700
16.67
1.34
0x31
28
700
2.95
2.25
1.45
0.75
350
3.3
2.6
1.8
1.1
600
800
33.33
2.50
0x32
32
800
2.9
2.13
1.4
0.65
400
3.3
2.5
1.8
1
600
900
50.00
3.52
0x33
36
900
2.85
1.954
1.35
0.454
450
3.3
2.4
1.8
0.9
600
1000
66.67
4.44
0x34
40
1000
2.8
1.84
1.3
0.34
500
3.3
2.3
1.8
0.8
600
1100
83.33
5.26
0x35
44
1100
2.75
1.654
1.25
0.154
550
3.3
2.2
1.8
0.7
600
1200
100.00
6.02
0x36
48
1200
2.7
1.54
1.2
04
600
3.3
2.13
1.8
0.65
1 Symbol definitions are shown in Table 20.
2 TX[A/B/C] level/PE control registers are port level control registers at Address 0x49, Address 0x89, and Address 0xC9. Per-lane level and PE control are in separate
registers.
3 This setting requires TX_HEADROOM = 1 to ensure adequate output compliance.
4 This setting is not recommended for ac-coupled outputs because the theoretical output low level is below the minimum output voltage limit listed in Table 1.
5 This setting is not recommended because the output level is below the minimum output voltage limit listed in Table 1. Use VCC = 2.5 V and TX_HEADROOM = 1.



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