AD9572ACPZLVD-R7 datasheet(6/20 Pages) AD

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AD9572

Rev. 0 | Page 6 of 20

CLOCK OUTPUTS

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given

over full VS and TA (−40°C to +85°C) variation.

Table 6.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL CLOCK OUTPUTS

Output Frequency

156.25

MHz

Output High Voltage (VOH)

VS − 1.24

VS − 1.05

VS − 0.83

Output Low Voltage (VOL)

VS − 2.07

VS − 1.87

VS − 1.62

Output Differential Voltage (VOD)

700

825

950

Duty Cycle

LVDS CLOCK OUTPUTS

Output Frequency

156.25

MHz

Differential Output Voltage (VOD)

250

350

475

Delta VOD

Output Offset Voltage (VOS)

1.125

1.25

1.375

Delta VOS

Short-Circuit Current (ISA, ISB)

Output shorted to GND

Duty Cycle

CMOS CLOCK OUTPUTS

Output Frequency

33.33

MHz

Output High Voltage (VOH)

VS − 0.1

Sourcing 1.0 mA current

Output Low Voltage (VOL)

0.1

Sinking 1.0 mA current

Duty Cycle

TIMING CHARACTERISTICS

Typical (typ) is given for VS = 3.3 V ± 10%, TA = 25°C, unless otherwise noted. Minimum (min) and maximum (max) values are given

over full VS and TA (−40°C to +85°C) variation.

Table 7.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL

Termination = 200 Ω to 0 V; CLOAD = 0 pF

Output Rise Time, tRP

480

625

810

20% to 80%, measured differentially

Output Fall Time, tFP

480

625

810

80% to 20%, measured differentially

LVDS

Termination = 100 Ω differential; CLOAD = 0 pF

Output Rise Time, tRL

160

350

540

20% to 80%, measured differentially

Output Fall Time, tFL

160

350

540

80% to 20%, measured differentially

CMOS

Termination = 50 Ω to 0 V; CLOAD = 5 pF

Output Rise Time, tRC

0.25

0.50

2.5

20% to 80%

Output Fall Time, tFC

0.25

0.70

2.5

80% to 20%

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