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AD9572ACPZLVD-R7 数据表(PDF) 11 Page - Analog Devices

部件名 AD9572ACPZLVD-R7
功能描述  Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9572ACPZLVD-R7 数据表(HTML) 11 Page - Analog Devices

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AD9572
Rev. 0 | Page 11 of 20
Pin No.
Mnemonic
Description
33
VS
Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers.
35
VS
Power Supply Connection for the FC VCO.
37
FORCE_LOW
Forces the 33.33 MHz output into a low state.
39
VS
Power Supply Connection for the FC PLL.
40
VS
Power Supply Connection for Miscellaneous Logic.
1 The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to
ground (GND).



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