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AD9572ACPZLVD-R7 数据表(PDF) 12 Page - Analog Devices

部件名 AD9572ACPZLVD-R7
功能描述  Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9572ACPZLVD-R7 数据表(HTML) 12 Page - Analog Devices

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AD9572
Rev. 0 | Page 12 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
Both 100 MHz and 125 MHz outputs enabled; 33.3 MHz output disabled.
–100
–150
–140
–130
–120
–110
–100
–160
–150
–140
–130
–120
–110
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
–160
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
Figure 7. 106.25 MHz Phase Noise
–100
–150
–140
–130
–120
–110
–160
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
Figure 8. 125 MHz Phase Noise
–100
–150
–140
–130
–120
–110
–160
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
Figure 9. 25 MHz Phase Noise
Figure 10. 156.25 MHz Phase Noise
–100
–160
–150
–140
–130
–120
–110
1k
10k
100k
1M
100M
10M
FREQUENCY (Hz)
Figure 11. 100 MHz Phase Noise



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