ADCLK948SLASHPCBZ datasheet(1/12 Pages) AD

部件名	ADCLK948/PCBZ

功能描述	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer

PDF	12 Pages

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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1 / 12 page

Two Selectable Inputs, 8 LVPECL Outputs,

SiGe Clock Fanout Buffer

ADCLK948

Rev. 0

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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No

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FEATURES

2 selectable differential inputs

4.8 GHz operating frequency

75 fs rms broadband random jitter

On-chip input terminations

3.3 V power supply

APPLICATIONS

Low jitter clock distribution

Clock and data signal restoration

Level translation

Wireless communications

Wired communications

Medical and industrial imaging

ATE and high performance instrumentation

GENERAL DESCRIPTION

The ADCLK948 is an ultrafast clock fanout buffer fabricated

on the Analog Devices, Inc., proprietary XFCB3 silicon german-

ium (SiGe) bipolar process. This device is designed for high

speed applications requiring low jitter.

The ADCLK948 is an ultrafast clock fanout buffer fabricated

on the Analog Devices, Inc., proprietary XFCB3 silicon german-

ium (SiGe) bipolar process. This device is designed for high

speed applications requiring low jitter.

The device has two selectable differential inputs via the IN_SEL

control pin. Both inputs are equipped with center tapped,

differential, 100 Ω on-chip termination resistors. The inputs

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A

VREFx pin is available for biasing ac-coupled inputs.

The device has two selectable differential inputs via the IN_SEL

control pin. Both inputs are equipped with center tapped,

differential, 100 Ω on-chip termination resistors. The inputs

accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),

and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A

VREFx pin is available for biasing ac-coupled inputs.

The ADCLK948 features eight full-swing emitter coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias VCC to the positive supply and VEE to ground. For ECL

operation, bias VCC to ground and VEE to the negative supply.

The ADCLK948 features eight full-swing emitter coupled logic

(ECL) output drivers. For LVPECL (positive ECL) operation,

bias VCC to the positive supply and VEE to ground. For ECL

operation, bias VCC to ground and VEE to the negative supply.

The output stages are designed to directly drive 800 mV each

side into 50 Ω terminated to VCC − 2 V for a total differential

output swing of 1.6 V.

The output stages are designed to directly drive 800 mV each

side into 50 Ω terminated to VCC − 2 V for a total differential

output swing of 1.6 V.

The ADCLK948 is available in a 32-lead LFCSP and specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

The ADCLK948 is available in a 32-lead LFCSP and specified

for operation over the standard industrial temperature range of

−40°C to +85°C.

FUNCTIONAL BLOCK DIAGRAM

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

LVPECL

ADCLK948

REFERENCE

VT0

VREF0

IN_SEL

CLK0

VT1

CLK1

VREF1

REFERENCE

Figure 1.

类似零件编号 - ADCLK948/PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	ADCLK948	427Kb / 5P	Increasing the Number of Outputs from a Clock Source Using Low Jitter LVPECL Fanout Buffers REV. 0
	ADCLK948	387Kb / 12P	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B
	ADCLK948BCPZ	387Kb / 12P	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B
	ADCLK948BCPZ-REEL7	387Kb / 12P	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B
	ADCLK948	387Kb / 12P	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B

More results

类似说明 - ADCLK948/PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	ADCLK946	476Kb / 12P	Six LVPECL Outputs, SiGe Clock Fanout Buffer REV. 0
	ADCLK950	879Kb / 12P	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer REV. 0
	ADCLK954	350Kb / 12P	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer REV. A
	ADCLK944	227Kb / 12P	2.5 V/3.3 V, Four LVPECL Outputs, SiGe Clock Fanout Buffer REV. 0
Cypress Semiconductor	CY2DP1504	301Kb / 14P	1:4 LVPECL Fanout Buffer with Selectable Clock Input
Integrated Device Techn...	ICS853S014I	248Kb / 20P	Two selectable differential LVPECL clock inputs
Analog Devices	ADCLK946	335Kb / 12P	Six LVPECL Outputs, SiGe Clock Fanout Buffer 8/2017-Rev. A to Rev. B
	ADCLK948	387Kb / 12P	Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B
	ADCLK950	389Kb / 12P	Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. A to Rev. B
	ADCLK954	386Kb / 12P	Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer 8/2016-Rev. B to Rev. C