ADCLK948

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FUNCTIONAL DESCRIPTION

CLOCK INPUTS

Thevenin-equivalent termination uses a resistor network to

the LVPECL driver. In this case, VS_DRV on the ADCLK948

combination shown (in Figure 15) results in a dc bias point of

VS_DRV − 2 V, the actual common-mode voltage is VS_DRV −

1.3 V because there is additional current flowing from the

ADCLK948 LVPECL driver through the pull-down resistor.

The ADCLK948 accepts a differential clock input from one of

two inputs and distributes the selected clock to all eight LVPECL

outputs. The maximum specified frequency is the point at which

the output voltage swing is 50% of the standard LVPECL swing

(see Figure 4). See the functional block diagram (Figure 1) and

the General Description section for more clock input details.

See Figure 19 through Figure 23 for various clock input

termination schemes.

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue.

Output jitter performance is degraded by an input slew rate

below 4 V/ns, as shown in Figure 12. The ADCLK948 is

specifically designed to minimize added random jitter over a

wide input slew rate range. Whenever possible, clamp excessively

large input signals with fast Schottky diodes because attenuators

reduce the slew rate. Input signal runs of more than a few

centimeters should be over low loss dielectrics or cables with

good high frequency characteristics.

CLOCK OUTPUTS

The specified performance necessitates using proper transmission

line terminations. The LVPECL outputs of the ADCLK948 are

designed to directly drive 800 mV into a 50 Ω cable or into

microstrip/stripline transmission lines terminated with 50 Ω

output stage is shown in Figure 13. The outputs are designed for

best transmission line matching. If high speed signals must be

routed more than a centimeter, either the microstrip or the

stripline technique is required to ensure proper transition times

and to prevent excessive output ringing and pulse width depen-

dent propagation delay dispersion.

Qx

Qx

Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage

Figure 14 through Figure 17 depict various LVPECL output

should match VS_DRV.

ADCLK948

VS_DRV

LVPECL

50Ω

50Ω

Figure 14. DC-Coupled, 3.3 V LVPECL

VS_DRV

50Ω

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

ADCLK948

LVPECL

127Ω

127Ω

83Ω

83Ω

Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination

ADCLK948

VS_DRV

LVPECL

50Ω

50Ω

50Ω

Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination

A

VS_DRV

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100Ω

0.1nF

0.1nF

DCLK948

200Ω

200Ω

Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line