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ADCLK948/PCBZ 数据表(PDF) 11 Page - Analog Devices

部件名 ADCLK948/PCBZ
功能描述  Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer
PDF  12 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCLK948/PCBZ 数据表(HTML) 11 Page - Analog Devices

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ADCLK948
Rev. 0 | Page 11 of
12
VREFx
INPUT TERMINATION OPTIONS
VCC
VTx
CLKx
VREFx
VTx
CLKx
CONNECT VTxTO VCC.
50Ω
50Ω
ADCLK948
Figure 19. DC-Coupled CML Input Termination
VREFx
VTx
VCC
50Ω
50Ω
CLKx
CLKx
0.01µF
(OPTIONAL)
50Ω
ADCLK948
Figure 20. DC-Coupled LVPECL Input Termination
CONNECT VTxTO VREFx.
50Ω
50Ω
CLKx
CLKx
ADCLK948
VREFx
VTx
Figure 21. AC-Coupled Input Termination, Such as LVDS and LEVPECL
CONNECT VTx, VREFx, AND CLKx. PLACE A
BYPASS CAPACITOR FROM VTx TO GROUND.
ALTERNATIVELY, VTx, VREFx, AND CLKx CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º
50Ω
50Ω
CLKx
CLKx
PHASE SHIFT.
ADCLK948
Figure 22. AC-Coupled Single-Ended Input Termination
VREFx
VTx
50Ω
50Ω
CLKx
CLKx
ADCLK948
Figure 23. DC-Coupled 3.3 V CMOS Input Termination



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