STM32F103XC datasheet(16/123 Pages) STMICROELECTRONICS

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Description

STM32F103xC, STM32F103xD, STM32F103xE

16/123

Doc ID 14611 Rev 7

2.3.6

LCD parallel interface

The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It

supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to

specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost-

effective graphic applications using LCD modules with embedded controllers or high-

performance solutions using external controllers with dedicated acceleration.

2.3.7

Nested vectored interrupt controller (NVIC)

The STM32F103xC, STM32F103xD and STM32F103xE performance line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

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Closely coupled NVIC gives low latency interrupt processing

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Interrupt entry vector table address passed directly to the core

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Closely coupled NVIC core interface

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Allows early processing of interrupts

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Processing of late arriving higher priority interrupts

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Support for tail-chaining

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Processor state automatically saved

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8

External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

2.3.9

Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock entry is available when necessary (for example with

failure of an indirectly used external oscillator).

Several prescalers allow the configuration of the AHB frequency, the high speed APB

(APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and

the high speed APB domains is 72 MHz. The maximum allowed frequency of the low speed

APB domain is 36 MHz. See Figure 2 for details on the clock tree.

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