MCP621 datasheet(4/44 Pages) MICROCHIP

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MCP621/2/5

DS22188A-page 4

Calibration Input

Calibration Input Voltage Range

VCALRNG

VSS +0.1

—

VDD –1.4

VCAL pin externally driven

Internal Calibration Voltage

VCAL

0.323VDD

0.333VDD

0.343VDD

VCAL pin open

Input Impedance

ZCAL

—

100 || 5

—

Ω||pF

Power Supply

Supply Voltage

VDD

2.5

—

5.5

Quiescent Current per Amplifier

1.2

2.5

3.6

IO = 0

POR Input Threshold, Low

VPRL

1.15

1.40

—

POR Input Threshold, High

VPRH

—

1.40

1.65

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CAL/CS =VSS (refer to Figure 1-2).

Parameters

Sym

Min

Typ

Max

Units

Conditions

AC Response

Gain Bandwidth Product

GBWP

—

MHz

Phase Margin

—

G = +1

Open-Loop Output Impedance

ROUT

—15—

AC Distortion

Total Harmonic Distortion plus Noise

THD+N

—

0.0018

—

G = +1, VOUT = 2VP-P, f = 1 kHz,

VDD = 5.5V, BW = 80 kHz

Step Response

Rise Time, 10% to 90%

—

G = +1, VOUT = 100 mVP-P

Slew Rate

—

V/µs

G = +1

Noise

Input Noise Voltage

Eni

—20—

µVP-P f = 0.1 Hz to 10 Hz

Input Noise Voltage Density

eni

—13—

nV/

√Hz f = 1 MHz

Input Noise Current Density

ini

4—

fA/

√Hz f = 1 kHz

DIGITAL ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,

VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CAL/CS =VSS (refer to Figure 1-1 and Figure 1-2).

Parameters

Sym

Min

Typ

Max

Units

Conditions

CAL/CS Low Specifications

CAL/CS Logic Threshold, Low

VIL

VSS

—0.2VDD

Note 1:

The MCP622 has its CAL/CS input internally pulled down to VSS (0V).

This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised

before the calibration is complete, the calibration will be aborted and the part will return to low power mode.

For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously

(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are

toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in

calibration mode; allow more than the maximum tCON time (8 ms) before the other side is toggled.

DC ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3,

VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CAL/CS =VSS (refer to Figure 1-2).

Parameters

Sym

Min

Typ

Max

Units

Conditions

Note 1:

Describes the offset (under the specified conditions) right after power up, or just after the CAL/CS pin is toggled. Thus,

1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.

Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.

See Figure 2-6 and Figure 2-7 for temperature effects.

The ISC specifications are for design guidance only; they are not tested.

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