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IMX35 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
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IMX35 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 148 page ![]() i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6 Freescale Semiconductor 39 Figure 18. Synchronous Memory Timing Diagram for Two Non-Sequential Read Accesses— WSC= 2, SYNC= 1, DOL = 0 Figure 19. Synchronous Memory TIming Diagram for Burst Write Access— BCS = 1, WSC = 4, SYNC = 1, DOL = 0, PSR = 1 Last Valid Addr Address V1 Address V2 V1 V1+2 V2 V2+2 BCLK ADDR ECB DATA Halfword Halfword CS[x] RW LBA OE EB[y] Halfword Halfword WE4 WE5 WE7 WE10 WE11 WE12 WE13 WE14 WE15 WE18, WE19 WE18, WE19 WE20, WE21 WE20, WE21 WE22, WE23 WE22, WE23 WE24, WE25 WE24, WE25 WE6 Last Valid Addr BCLK ADDR DATA CS[x] RW LBA OE EB[y] ECB Address V1 V1 V1+4 V1+12 V1+8 WE12 WE4 WE5 WE6 WE7 WE8 WE9 WE13 WE14 WE16 WE16 WE17 WE17 WE22, WE23 WE24, WE25 WE15 |
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