IMX35 datasheet(69/148 Pages) FREESCALE

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i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6

Freescale Semiconductor

4.9.13.1

Synchronous Interfaces

This section discusses the interfaces to active matrix TFT LCD panels, Sharp HR-TFT, and dual-port smart

displays.

4.9.13.1.4

Interface to Active Matrix TFT LCD Panels, Functional Description

Figure 48 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,

signals are shown with negative polarity. The sequence of events for active matrix interface timing is as

follows:

•

DISPB_D3_CLK latches data into the panel on its negative edge (when positive polarity is

selected). In active mode, DISPB_D3_CLK runs continuously.

•

DISPB_D3_HSYNC causes the panel to start a new line.

•

DISPB_D3_VSYNC causes the panel to start a new frame. It always encompasses at least one

HSYNC pulse.

•

DISPB_D3_DRDY acts like an output enable signal to the CRT display. This output enables the

data to be shifted to the display. When disabled, the data is invalid and the trace is off.

Figure 48. Interface Timing Diagram for TFT (Active Matrix) Panels

4.9.13.1.5

Interface to Active Matrix TFT LCD Panels, Electrical Characteristics

Figure 49 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and

the data. All figure parameters shown are programmable. The timing images correspond to inverse polarity

DISPB_D3_CLK

123

m–1

DISPB_D3_HSYNC

DISPB_D3_VSYNC

DISPB_D3_HSYNC

LINE 1

LINE 2

LINE 3

LINE 4

LINE n – 1

LINE n

DISPB_D3_DRDY

DISPB_D3_DATA

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