ADN2531

Rev. 0 | Page 16 of 20

perates,

CB layout to obtain

n

en

se multiple capacitors in

FP+ and XFP modules, contact sales. For guidelines on the

rface-mount assembly of the ADN2531, see the AN-772

Application Note, A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP)

DESIGN EXAMPLE

Assuming that the impedance of the TOSA is 12 Ω, the forward

•

The headroom for the IBIAS, IMODP, and IMODN pins.

•

The typical voltage required at the BSET and MSET pins to

produce the desired bias and modulation currents.

•

Headroom Calculations

To ensure proper device operation, the voltages on the IBIAS,

IMODP, and IMODN pins must meet the compliance voltage

specifications in Table 1.

Considering the typical application circuit shown in Figure 40,

the voltage at the IBIAS pin can be written as

e:

CC

is the supply voltage.

is the forward voltage across the laser at low current.

is the resistance of the TOSA.

is the dc voltage drop across L5, L6, L7, and L8.

For proper operation, the minimum voltage at the IBIAS pin

should be greater than 0.6 V, as specified by the minimum

IBIAS compliance specification in Table 1.

Assuming that the voltage drop across the 50 Ω transmission lines

= 3.3 − 1.5 − (0.04 × 12) = 1.32 V

COMPLIANCE_MAX

CC

atisfies the

ulate the h

a

urrent pins

IMO

he

CC

e to the ac-co

led

0 Ω becau

is

roper

operation of the ADN2531, t

pin should

in

region shown

in Figure 36.

ing the dc

ltage dro

mA,

nim

odulation

qual

requirement.

The maximum voltage at the modulation output pins is equal to

requirement.

Headroom calculations must be repeated for the minimum and

proper device operation over all operating conditions.

BSET and MSET Pin Voltage Calculations

To set the desired bias and modulation currents, the BSET and

MSET pins of the ADN2531 must be driven with the appropriate

dc voltage. The voltage range required at the BSET pin to generate

BSET voltage is given by

LAYOUT GUIDELINES

Due to the high frequencies at which the ADN2531 o

care should be taken when designing the P

optimum performance. For example, use controlled impedance

transmission lines for high speed signal paths, and keep the

length of transmission lines as short as possible to reduce losses

and pattern-dependent jitter. In addition, the PCB layout must

be symmetrical, both on the DATAP and DATAN inputs and o

the IMODP and IMODN outputs, to ensure a balance between

the differential signals.

Furthermore, all VCC and GND pins must be connected to

solid copper planes by using low inductance connections. Wh

these connections are made through vias, multiple vias can be

connected in parallel to reduce the parasitic inductance. Each

GND pin must be locally decoupled to VCC with high quality

capacitors (see Figure 40). If proper decoupling cannot be

achieved using a single capacitor, u

parallel for each GND pin. A 20 μF tantalum capacitor must be

used as the general decoupling capacitor for the entire module.

For recommended PCB layouts, including those suitable for the

The maximum voltage at the IBIAS pin must be less than the

maximum IBIAS compliance specification as described by

For this example,

V

= V

− 0.75 − 4.4 × 0.04 = 2.374 V

S

su

wher

V

requirement.

To calc

eadroom t the modulation c

(IMODP and

to V

du

DN), t

up

voltage has a dc component equal

configuration and a swing equal to

less than 100 Ω. For p

he voltage at each modulation

output

be with

the normal operation

Assum

vo

p across L1, L2, L3, and L4 is 0 V

output pins is e

the mi

to

um voltage at the m

V

4

.

0

100

40

mA/V

100

BSET

V

(mA)

=

=

I

The BSET voltage range can be calculated using the required

The voltage required at the MSET pin to produce the desired

modulation current can be calculated using

K

I

V

MOD