ATmega162 datasheet(65/324 Pages) ATMEL

65 / 324 page

2513K–AVR–07/09

ATmega162/V

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b11) as an intermediate step.

Table 27 summarizes the control signals for the pin value.

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 29, the PINxn Register bit and the preceding latch consti-

tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near

the edge of the internal clock, but it also introduces a delay. Figure 30 shows a timing diagram of

the synchronization when reading an externally applied pin value. The maximum and minimum

propagation delays are denoted t

pd,max and tpd,min respectively.

Figure 30. Synchronization when Reading an Externally Applied Pin Value

Table 27. Port Pin Configurations

DDxn

PORTxn

PUD

(in SFIOR)

I/O

Pull-up

Comment

Input

Tri-state (Hi-Z)

Input

Yes

Pxn will source current if ext. pulled

low.

Input

Tri-state (Hi-Z)

Output

Output Low (Sink)

Output

Output High (Source)

XXX

in r17, PINx

0x00

0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

tpd, max

tpd, min

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