HT56R656 datasheet(63/108 Pages) HOLTEK

63 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

¨ SIMIDLE

The SIMIDLE bit is used to select if the I

2C interface

continues running when the device is in the IDLE

mode. Setting the bit high allows the I

2C interface to

maintain operation when the device is in the Idle

mode. Clearing the bit to zero disables any I

2Cop-

erations when in the Idle mode.

This SPI/I

2C idle mode control bit is located at

CLKMOD register bit4.

¨ SIMEN

The SIMEN bit is the overall on/off control for the I

interface. When the SIMEN bit is cleared to zero to

disable the I

2C interface, the SDA and SCL lines will

be in a floating condition and the I

2C operating cur-

rent will be reduced to a minimum value. In this con-

dition the pins can be used as SEG functions. When

the bit is high the I

2C interface is enabled. The SIM

configuration option must have first enabled the SIM

interface for this bit to be effective. Note that when

the SIMENbit changes from low to high the contents

of the I

2C control registers will be in an unknown

condition and should therefore be first initialised by

the application program

¨ SIM0~SIM2

These bits setup the overall operating mode of the

SIM function. To select the I

2C function, bits SIM2~

SIM0 should be set to the value 110.

¨ RXAK

The RXAK flag is the receive acknowledge flag.

When the RXAK bit has been reset to zero it means

that a correct acknowledge signal has been re-

ceived at the 9th clock, after 8 bits of data have

been transmitted. When in the transmit mode, the

transmitter checks the RXAK bit to determine if the

receiver wishes to receive the next byte. The trans-

mitter will therefore continue sending out data until

the RXAK bit is set high. When this occurs, the

transmitter will release the SDA line to allow the

master to send a STOP signal to release the bus.

¨ SRW

The SRW bit is the Slave Read/Write bit. This bit de-

termines whether the master device wishes to

transmit or receive data from the I

2C bus. When the

transmitted address and slave address match, that

is when the HAAS bit is set high, the device will

check the SRW bit to determine whether it should

be in transmit mode or receive mode. If the SRW bit

is high, the master is requesting to read data from

the bus, so the device should be in transmit mode.

When the SRW bit is zero, the master will write data

to the bus, therefore the device should be in receive

mode to read this data.

¨ TXAK

The TXAK flag is the transmit acknowledge flag. Af-

ter the receipt of 8-bits of data, this bit will be trans-

mitted to the bus on the 9th clock. To continue

receiving more data, this bit has to be reset to zero

before further data is received.

¨ HTX

The HTX flag is the transmit/receive mode bit. This

flag should be set high to set the transmit mode and

low for the receive mode.

¨ HBB

The HBB flag is the I

2C busy flag. This flag will be

high when the I

2C bus is busy which will occur when

a START signal is detected. The flag will be reset to

zero when the bus is free which will occur when a

STOP signal is detected.

¨ HASS

The HASS flag is the address match flag. This flag

is used to determine if the slave device address is

the same as the master transmit address. If the ad-

dresses match then this bit will be high, if there is no

match then the flag will be low.

¨ HCF

The HCF flag is the data transfer flag. This flag will

be zero when data is being transferred. Upon com-

pletion of an 8-bit data transfer the flag will go high

and an interrupt will be generated.

I 2 C D a t a R e g i s t e r

( S I M D R )

S l a v e A d d r e s s R e g i s t e r

( S I M A R )

S h i f t R e g i s t e r

D i r e c t i o n C o n t r o l

A d d r e s s M a t c h

H A A S B i t

I 2 C I n t e r r u p t

D a t a i n L S B

D a t a O u t M S B

T r a n s m i t / R e c e i v e

C o n t r o l U n i t

8 - b i t D a t a C o m p l e t e

D e t e c t S t a r t o r S t o p

D a t a B u s

A d d r e s s

C o m p a r a t o r

E n a b l e / D i s a b l e A c k n o w l e d g e

R e a d / w r i t e S l a v e

S R W B i t

H B B B i t

H T X B i t

S C L P i n

S D A P i n

H C F B i t

2C Block Diagram

HT56R656 数据表(PDF) 63 Page - Holtek Semiconductor Inc

HT56R656 数据表(HTML) 63 Page - Holtek Semiconductor Inc

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