HT56R656 datasheet(29/108 Pages) HOLTEK

29 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

I/O Port Control Registers

Each I/O port has its own control register known as PAC,

PBC and PDC, to control the input/output configuration.

With this control register, each CMOS output or input

with or without pull-high resistor structures can be re-

configured dynamically under software control. Each pin

of the I/O ports is directly mapped to a bit in its associ-

ated port control register. For the I/O pin to function as

an input, the corresponding bit of the control register

must be written as a

²1². This will then allow the logic

state of the input pin to be directly read by instructions.

When the corresponding bit of the control register is

written as a

²0², the I/O pin will be setup as a CMOS out-

put. If the pin is currently setup as an output, instructions

can still be used to read the output register. However, it

should be noted that the program will in fact only read

the status of the output data latch and not the actual

logic status of the output pin.

Pin-shared Functions

The flexibility of the microcontroller range is greatly en-

hanced by the use of pins that have more than one func-

tion. Limited numbers of pins can force serious design

constraints on designers but by supplying pins with

multi-functions, many of these difficulties can be over-

come. For some pins, the chosen function of the

multi-function I/O pins is set by configuration options

while for others the function is set by application pro-

gram control.

· External Interrupt Inputs

The external interrupt pins INT0, INT1 are pin-shared

with the I/O pins PD4, PD5. For applications not re-

quiring an external interrupt input, the pin-shared ex-

ternal interrupt pin can be used as a normal I/O pin,

however to do this, the external interrupt enable bits in

the INTC0 register must be disabled.

· External Timer Clock Input

The external timer pins TMR0, TMR1 and TMR2 are

pin-shared with I/O pins. To configure them to operate

as timer inputs, the corresponding control bits in the

timer control register must be correctly set and the pin

must also be setup as an input. Note that the original

I/O function will remain even if the pin is setup to be

used as an external timer input.

· PFD Output

The device contains a PFD function whose single out-

put is pin-shared with I/O pin PA3. The output function

of this pin is chosen via a configuration option and re-

mains fixed after the device is programmed. Note that

the corresponding bit of the port control register,

PAC.3, must setup the pin as an output to enable the

PFD output. If the PAC port control register has setup

the pin as an input, then the pin will function as a nor-

mal logic input with the usual pull-high selection, even

if the PFD configuration option has been selected.

· PWM Outputs

The device contains several PWM outputs shared

with pins PD0~PD3. The PWM output functions are

chosen via registers. Note that the corresponding bit

of the port control register, PDC, must setup the pin as

an output to enable the PWM output. If the PDC port

control register has setup the pin as an input, then the

pin will function as a normal logic input with the usual

pull-high selection, even if the PWM registers have

enabled the PWM function.

· A/D Inputs

The device contains a multi-channel A/D converter in-

puts. All of these analog inputs are pin-shared with I/O

pins on Port B. If these pins are to be used as A/D in-

puts and not as normal I/O pins then the corresponding

bits in the A/D Converter Control Register, ADCR, must

be properly set. There are no configuration options as-

sociated with the A/D function. If used as I/O pins, then

full pull-high resistor register remain, however if used

as A/D inputs then any pull-high resistor selections as-

sociated with these pins will be automatically discon-

nected.

I/O Pin Structures

The accompanying diagrams illustrate the internal

structures of some I/O pin types. As the exact logical

construction of the I/O pin will differ from these draw-

ings, they are supplied as a guide only to assist with the

functional understanding of the I/O pins. The wide range

of pin-shared structures does not permit all types to be

shown.

P A P U , P B P U , P D P U R e g i s t e r

P A . 0 , P B . 0 , P D . 0 P u l l - h i g h

1 : e n a b l e

0 : d i s a b l e

P A . 1 , P B . 1 , P D . 1 P u l l - h i g h

1 : e n a b l e

0 : d i s a b l e

P A . 7 , P B . 7 , P D . 7 P u l l - h i g h

1 : e n a b l e

0 : d i s a b l e

b 7

P X P U 0

b 0

P X P U 1

P X P U 7

Pull-High Resistor Register

- PAPU, PBPU, PDPU

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