HT56R656 datasheet(33/108 Pages) HOLTEK

33 / 108 page

HT56R62/HT56R65

HT56R642/HT56R644/HT56R654/HT56R656

Rev. 1.00

July 20, 2009

LCD/LED Registers

Control Registers in the Data Memory, are used to con-

trol the various setup features of the LCD/LED Driver.

There is one control register for the LCD function,

LCDCTRL, and one for the LED function, LEDCTRL.

Various bits in these registers control functions such as

duty type, bias type, bias resistor selection as well as

overall LCD enable and disable. The LEDSEL bit in the

LEDCTRL register must be first setup to determine

whether the display is an LED or LCD type. Pro-

gramming this bit will determine what other options are

available. The LCDEN bit in the LCDCTRL and LEDEN

bit in the LEDCTRL register, which provide the overall

LCD/LED enable/disable function, will only be effective

when the device is in the Normal, Slow or Idle Mode. If

the device is in the Sleep Mode then the display will al-

ways be disabled. Bits RSEL0 and RSEL1 in the

LCDCTRL register select the internal bias resistors to

supply the LCD panel with the correct bias voltages. A

choice to best match the LCD panel used in the applica-

tion can be selected also to minimise bias current. The

TYPE bit in the same register is used to select whether

Type A or Type B LCD control signals are used.

Two registers, LCDOUT1 and LCDOUT2 are used to

determine if the output function of display pins SEG0~

SEG23 are used as segment drivers or CMOS outputs.

If used as CMOS outputs then the Display Memory is

used to determine the logic level of the CMOS output

pins. Note that as only two bits are used to determine

the output function of the SEG0~SEG7 and

SEG8~SEG15 pins, individual pins from these two

groups of pins cannot be chosen to have either a seg-

ment or CMOS output function. The output function of

pins SEG16~SEG23 can be chosen individually to be

either a segment driver or a CMOS input.

LCD Reset Function

The LCD has an internal reset function that is an OR

function of the inverted LCDEN bit in the LCDCTRL reg-

ister and the Sleep function. The LCD reset signal is ac-

tive high. The LCDEN signal is the inverse of the

LCDEN bit in the LCDCTRL register.

Reset LCD = (Sleep Mode AND LCDEN) OR LCDEN.

LCDEN =0 and LCDEN =1 must be enabled to activate

the LCDCTRL register function.

LCDEN

Sleep Mode

Reset LCD

Off

0On

Off

1On

LCD Reset Function

Clock Source

The LCD clock source is the internal clock signal, fSUB,

divided by 8, using an internal divider circuit. The fSUB in-

ternal clock is supplied by either the internal 32K_INT

oscillator or the external 32768Hz oscillator, the choice

of which is determined by a configuration option. For

proper LCD operation, this arrangement is provided to

generate an ideal LCD clock source frequency of 4kHz.

fSUB Clock Source

LCD Clock Frequency

Internal 32K_INT Osc.

4kHz

External 32768Hz Osc.

4kHz

LCD Clock Source

LCD Driver Output

When the LEDSEL bit in the LEDCTRL register is

cleared to zero, the COM and SEG lines will be setup as

LCD driver pins to drive the LCD display.

The number of COM and SEG outputs supplied by the

LCD driver, as well as its biasing and duty selections,

are dependent upon how the LCD control bits are pro-

grammed. The Bias Type, whether C or R type is se-

lected using a configuration option.

If the C-type of bias is used when an internal charge

pump will be enabled. Note that the C-type bias is not

available on the 52-pin QFP package type.

The nature of Liquid Crystal Displays require that only

AC voltages can be applied to their pixels as the applica-

tion of DC voltages to LCD pixels may cause permanent

damage. For this reason the relative contrast of an LCD

display is controlled by the actual RMS voltage applied

to each pixel, which is equal to the RMS value of the

voltage on the COM pin minus the voltage applied to the

SEG pin. This differential RMS voltage must be greater

than the LCD saturation voltage for the pixel to be on

and less than the threshold voltage for the pixel to be off.

The requirement to limit the DC voltage to zero and to

control as many pixels as possible with a minimum num-

ber of connections, requires that both a time and ampli-

tude signal is generated and applied to the application

LCD. These time and amplitude varying signals are au-

tomatically generated by the LCD driver circuits in the

microcontroller. What is known as the duty determines

the number of common lines used, which are also

known as backplanes or COMs. The duty, which is cho-

sen by a control bit to have a value of 1/2, 1/3, 1/4 etc

and which equates to a COM number of 2, 3, 4 etc,

therefore defines the number of time divisions within

each LCD signal frame. Two types of signal generation

are also provided, known as Type A and Type B, the re-

quired type is selected via

the TYPE bit in the

LCDCTRL register. Type B offers lower frequency sig-

nals, however lower frequencies may introduce flicker-

ing and influence display clarity.

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