HT82M9AE datasheet(9/46 Pages) HOLTEK

9 / 46 page

HT82M9AE/HT82M9AA

Rev. 1.90

October 21, 2009

Interrupt

The device provides an external interrupt and internal

timer/event counter interrupts. The Interrupt Control

to set the enable/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all the other in-

terrupts will be blocked (by clearing the EMI bit). This

scheme may prevent any further interrupt nesting. Other

interrupt requests may occur during this interval but only

the interrupt request flag is recorded. If a certain inter-

rupt requires servicing within the service routine, the

EMI bit and the corresponding bit of the INTC may be

set to allow interrupt nesting. If the stack is full, the inter-

rupt request will not be acknowledged, even if the re-

lated interrupt is enabled, until the SP is decremented. If

immediate service is desired, the stack must be pre-

vented from becoming full.

All these kinds of interrupts have a wake-up capability.

As an interrupt is serviced, a control transfer occurs by

pushing the program counter onto the stack, followed by

a branch to a subroutine at a specified location in the

program memory. Only the program counter is pushed

onto the stack. If the contents of the register or status

program which corrupts the desired control sequence,

the contents should be saved in advance.

The USB interrupts are triggered by the following USB

events and the related interrupt request flag (USBF; bit

4 of the INTC) will be set.

· Access of the corresponding USB FIFO from PC

· The USB suspend signal from PC

· The USB resume signal from PC

· USB Reset signal

When the interrupt is enabled, the stack is not full and

the external interrupt is active, a subroutine call to loca-

tion 04H will occur. The interrupt request flag (USBF)

and EMI bits will be cleared to disable other interrupts.

When the PC Host access the FIFO of the HT82M9AE/

HT82M9AA, the corresponding request bit of the USR is

set, and a USB interrupt is triggered. So user can easily

decide which FIFO is accessed. When the interrupt has

been served, the corresponding bit should be cleared by

firmware. When the HT82M9AE/HT82M9AA receives a

USB Suspend signal from the Host PC, the suspend line

(bit0 of the USC) of the HT82M9AE/HT82M9AA is set

and a USB interrupt is also triggered.

Bit No.

Label

Function

EMI

Controls the master (global) interrupt (1=enable; 0=disable)

EUI

Controls the USB interrupt (1=enable; 0= disable)

2, 5, 7

Unused bit, read as

²0²

ETI

Controls the Timer/Event Counter interrupt (1=enable; 0=disable)

USBF

USB interrupt request flag (1=active; 0=inactive)

Internal timer/event counter request flag (1:active; 0:inactive)

INTC (0BH) Register

Bit No.

Label

Function

C is set if an operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate

through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

PDF

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by

executing the

²HALT² instruction.

5TO

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6~7

Unused bit, read as

²0²

Status (0AH) Register

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