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HT82M9AE 数据表(PDF) 13 Page - Holtek Semiconductor Inc |
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HT82M9AE 数据表(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 46 page  HT82M9AE/HT82M9AA Rev. 1.90 13 October 21, 2009 The registers status are summarized in the following table. Register Reset (Power On) WDT Time-out (Normal Operation) RES Reset (Normal Operation) RES Reset (HALT) WDT Time-Out (HALT)* USB-Reset (Normal) USB-Reset (HALT) TMRH xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu TMRL xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu TMRC 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- 00-0 1--- 00-0 1--- Program Counter 000H 000H 000H 000H 000H 000H 000H MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu BP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu TBHP xxxx xxxx 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu 0000 uuuu STATUS --00 xxxx --1u uuuu --00 uuuu --00 uuuu --11 uuuu --uu uuuu --01 uuuu INTC -000 0000 -000 0000 --00 uuuu -000 0000 -uuu uuuu -000 0000 -000 0000 WDTS 1000 0111 1000 0111 1000 0111 1000 0111 uuuu uuuu 1000 0111 1000 0111 PA 1111 1111 xxxx xxxx 1111 1111 1111 1111 xxxx xxxx 1111 1111 1111 1111 PAC 1111 1111 xxxx xxxx 1111 1111 1111 1111 xxxx xxxx 1111 1111 1111 1111 PB 1111 1111 xxxx xxxx 1111 1111 1111 1111 xxxx xxxx 1111 1111 1111 1111 PBC 1111 1111 xxxx xxxx 1111 1111 1111 1111 xxxx xxxx 1111 1111 1111 1111 AWR 0000 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 STALL 0000 0110 0000 uuuu 0000 1110 0000 1110 0000 uuuu 0000 0000 0000 0000 SIES 0100 0000 uuuu uuuu 0100 0000 0100 0000 uuuu uuuu 0000 0000 0000 0000 MISC 0x00 0000 uuuu uuuu 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 FIFO0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 FIFO1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 FIFO2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 0000 0000 Pipe_ctrl 0000 0110 0000 0uuu 0000 0110 0000 0110 0000 0110 0000 0110 0000 0110 Endpt_EN 0000 0111 0000 0uuu 0000 0111 0000 0111 0000 0111 0000 0111 0000 0111 USC 11xx 0000 11xx xuux 11xx 0000 11xx 0000 11xx xuux 1100 0u00 1100 0u00 USR 0000 0000 u0uu 0u00 0000 0000 0000 0000 u0uu uuuu u1uu 0000 u1uu 0000 SCC 0000 0000 uu00 u000 0000 0000 0000 0000 uu0u u000 uu00 u000 uu00 u000 Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² |
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