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AS1100PL 数据表(PDF) 2 Page - ams AG

部件名 AS1100PL
功能描述  Serially Interfaced, 8-Digit LED Driver
PDF  17 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1100PL 数据表(HTML) 2 Page - ams AG

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www.austriamicrosystems.com
Revision 1.33
2 - 17
AS1100
Data Sheet - P i n A s s i g n m e n t s
4 Pin Assignments
Figure 2. Pin Assignments (Top View)
Pin Descriptions
Table 1. Pin Descriptions
Pin
Name
Pin
Number
Description
DIN
1
Data input. Data is programmed into the 16Bit shift register on the rising
CLK edge
DIG 0 – DIG 7
2, 3, 5–8,
10, 11
8 digit driver lines that sink the current from the common cathode of the
display. In shutdown mode the AS1100 switches the outputs to VDD.
GND
4, 9
Both GND pins must be connected.
LOAD/CS
12
Strobe input. With the rising edge of the LOAD signal the 16 bit of serial
data is latched into the register.
CLK
13
Clock input. The interface is capable to support clock frequencies up to
10MHz. The serial data is clocked into the internal shift register with the
rising edge of the CLK signal. On the DOUT pin the data is applied with the
falling edge of CLK.
SEG A–G, DP
14–17,
20–23
Seven segment driver lines including the decimal point. When a
segment is turned off the output is connected to GND.
ISET
18
The current into ISET determines the peak current through the segments
and therefore the brightness.
VDD
19
Positive Supply Voltage (+5V)
DOUT
24
Serial data output for cascading drivers. The output is valid after 16.5
clock cycles. The output is never set to high impedance.
DIP/SO
11
12
13
14
15
16
17
18
19
20
21
22
23
DIG4
AS1100
10
1
2
3
4
5
6
7
8
9
24 DOUT
DIN
DIG0
GND
DIG6
DIG2
GND
DIG3
LOAD
SEG D
SEG DP
SEG E
SEG C
VDD
ISET
SEG G
SEG B
SEG F
SEG A
TOP
CLK
DIG7
DIG5
DIG1



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