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AS1100PL 数据表(PDF) 4 Page - ams AG

部件名 AS1100PL
功能描述  Serially Interfaced, 8-Digit LED Driver
PDF  17 Pages
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制造商  AMSCO [ams AG]
网页  http://www.ams.com
标志 AMSCO - ams AG

AS1100PL 数据表(HTML) 4 Page - ams AG

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www.austriamicrosystems.com
Revision 1.33
4 - 17
AS1100
Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s
6 Electrical Characteristics
VDD = 5V, RSET = 9.53k
Ω±1%, TA = TMIN to TMAX, unlesss otherwise noted.
Table 3. Electrical Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VDD
Operating Supply Voltage
4.0
5.0
5.5
V
IDDSD
Shutdown Supply Current
All digital inputs at VDD or GND,
TA = +25ºC
20
50
µA
IDD
Operating Supply Current
RSET = open circuit
500
µA
All segments and decimal point on,
ISEG = -40mA
330
mA
fOSC
Display Scan Rate
8 digits scanned
500
800
1300
Hz
IDIGIT
Digit Drive Sink Current
VOUT = 0.65V
320
mA
ISEG
Segment Drive Source Current
TA = +25ºC, VOUT = (VDD -1V)
-30
-40
-45
mA
ΔISEG
Segment Drive Current
Matching
3.0
%
IDIGIT
Digit Drive Source Current
Digit off, VDIGIT = (VDD -0.3V)
-2
mA
ISEG
Segment Drive Sink Current
Segment off, VSEG = 0.3V
5
mA
Logic Inputs
IIH, IIL
Input Current DIN, CLK, LOAD
VIN = 0V or VDD
-1
1
µA
VIH
Logic High Input Voltage
3.5
V
VIL
Logic Low Input Voltage
0.8
V
VOH
Output High Voltage
DOUT, ISOURCE = -1mA
VDD - 1
V
VOL
Output Low Voltage
DOUT, ISINK = 1.6mA
0.4
V
Hysteresis Voltage
DIN, CLK, LOAD
1
V
Timing Characteristics
tCP
CLK Clock Period
100
ns
tCH
CLK Pulse Width High
50
ns
tCL
CLK Pulse Width Low
50
ns
tCSH
CLK Rise to LOAD Rise Hold
Time
0ns
tDS
DIN Setup Time
25
ns
tDH
DIN Hold Time
0
ns
tDO
Output Data Propagation Delay
CLOAD = 50pF
25
ns
tLDCK
LOAD Rising Edge to Next
Clock Rising Edge
50
ns
tCSW
Minimum LOAD Pulse High
50
ns
tDSPD
Data-to-Segment Delay
2.25
ms



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