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AS3525 数据表(PDF) 75 Page - ams AG |
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AS3525 数据表(HTML) 75 Page - ams AG |
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75 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 75 - 194 Table 57 NAF control register Name Base Default NAFControl AS3525_NAND_FLASH_BASE 0x2 NAFControl Register Offset 0x0004 The NAFControl register controls read access and FIFO dynamic reset. Bit Bit Name Default Access Bit Description 1 read_strobe 0x1 W 1: triggers a FIFO reset pulse (when NAFConfig bit ‘fifo_staticreset_n’ is 1) The bit is cleared automatically in the next PCLK cycle. 0 fifo_reset_strobe 0x1 W 1: triggers one single read cycle on output ‘naf_re_n’. The bit is cleared automatically in the next PCLK cycle. |
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