AS3525 datasheet(19/194 Pages) AMSCO

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AS3525-A/-B C22O22

Data Sheet, Confidential

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Revision 1.13

- 194

7.1.3 ARM922T Details

The ARM922T macrocell is based on the ARM9TDMI Harvard

architecture processor core with an efficient five-stage pipeline.

To reduce the effect of memory bandwidth and latency on

performance, the ARM922T macrocell includes separate cachs

and MMUs for both instructions and data. It also has a write

buffer and physical address TAG RAM.

Caches

Two 8KB caches are implemented, one for instructions, the

other for data, both with an 8-word line size. Separate buses

connect each cache to the ARM9TDMI core permitting a 32 bit

instruction to be fetched and fed into the Decode stage of the

pipeline at the same time as a 32 bit data access for the

memory stage of the pipeline.

Cache lock-down is provided to permit critical code sequences

to be locked into the cache to ensure predictability for real-time

code. The cache replacement algorithm can be selected by the

operating system as either pseudo-random or round-robin. Both

caches are 64-way set-associative. Lock-down operates on a

per-way basis.

Write Buffer

The ARM922T macrocell also incorporates a 16-data, 4-

address write buffer to avoid stalling the processor when writes

to external memory are performed.

PA TAG RAM

The ARM922T macrocell implements a physical address TAG

RAM (PA TAG RAM) to perform write-backs from the data

cache.

The physical addresses of all the lines held in the data cache

are stored by the PA TAG memory, removing the requirement

for address translation when evicting a line from the cache.

MMU

The ARM922T macrocell implements an enhanced ARMv4

MMU to provide translation and access permission checks for

the instruction and data address ports of the ARM9TDMI core.

The MMU features are:

•

Standard ARMv4 MMU mapping sizes, domains,

and access protection scheme

•

Mapping sizes are 1 MB sections, 64 KB large

pages, 4 KB small pages, and new 1KB tiny pages

•

Access permissions for sections

•

Access permissions for large pages and small

pages can be specified separately for each quarter

of the page (subpages)

•

Access permissions for tiny pages

•

16 domains implemented in hardware

•

64-entry instruction Translation-Lookaside-Buffer

(TLB) and 64-entry data TLB

•

Hardware page table walks

•

Round-robin replacement algorithm (also called

cyclic)

Control Coprocessor (CP15)

The control coprocessor is provided for configuration of the caches, the

write buffer, and other ARM922T options.

Eleven registers are available for program control:

•

endianness, cache, and MMU enable

•

operations

•

operations

•

Debug Features

The ARM9TDMI processor core incorporates an EmbeddedICE unit and

EmbeddedICE-RT logic permitting both software tasks and external

debug hardware to

•

Set hardware and software breakpoints

•

Perform single-stepping

•

Enable access to registers and memory

This functionality is implemented as a coprocessor and is accessible

from hardware through the JTAG port.

Full-speed, real-time execution of the processor is maintained until a

breakpoint is hit.

At this point control is passed either to a software handler or to JTAG

control.

7.1.4 ARM V4T Architecture

The ARM9TDMI processor core implements the ARMv4T Instruction Set

Architecture (ISA). The ARMv4T ISA is a superset of the ARMv4 ISA

with additional support for the Thumb 16-bit compressed instruction set.

Performance and Code Density

The ARM9TDMI core executes two instruction sets

•

32-bit ARM instruction set

•

16-bit Thumb instruction set

The ARM instruction set is designed so that a program can achieve

maximum performance with the minimum number of instructions. Most

ARM9TDMI instructions are executed in a single cycle.

The simpler Thumb instruction set offers much increased code density

deducing code size and memory requirement.

Code can switch between the ARM and Thumb instruction sets on any

procedure call.

ARM9TDMI Integer Pipeline Stages

The integer pipeline consists of five stages to maximize instruction

throughput in the ARM9TDMI core:

•

Fetch

•

Decode and register read

•

Execute shift and ALU operation, or address calculate, or

multiply

•

Memory access and multiply

•

Write register

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