 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AS3525 数据表(PDF) 45 Page - ams AG |
|
|
|||||||||||||||||||||||||||||
AS3525 数据表(HTML) 45 Page - ams AG |
|
|
45 / 194 page  AS3525-A/-B C22O22 Data Sheet, Confidential © 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved. www.austriamicrosystems.com Revision 1.13 45 - 194 Watchdog control register, WdogControl This is a read/write register that enables the software to control the watchdog unit. Table 23 watchdog control register Name Base Default WdogControl AS3525_WDT_BASE 0x04 Watchdog Control Register Offset: 0x08 Bit Bit Name Default Access Bit Description 1 RESEN 0 R/W Enable Watchdog reset output (WDOGRES). Acts as a mask for the reset output. 0: disable the reset 1: enable the reset 0 INTEN 0 R/W Enable the interrupt event (WDOGINT). 0: disable the counter and interrupt 1: enable the counter and interrupt Watchdog clear interrupt register, WdogIntClr A write of any value to this location clears the watchdog interrupt, and reloads the counter from the value in WdogLoad. Raw interrupt status register, WdogRIS This register indicates the raw interrupt status from the counter. This value is ANDed with the inerrupt enable bit from the control register to create the masked interrupt, which is passed to the interrupt output pin. Table 24 watchdog raw interrupt status register Name Base Default WdogRIS AS3525_WDT_BASE Watchdog interrupt status register Offset: 0x10 Bit Bit Name Default Access Bit Description 0 Watchdog Interrupt R Enabled interrupt status from the counter Interrupt status register, WdogMIS This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the INTEN bit from the control register, and is the same value which is passed to the interrupt output pin. Name Base Default WdogMIS AS3525_WDT_BASE Watchdog raw interrupt status register Offset: 0x14 Bit Bit Name Default Access Bit Description 0 Raw Watchdog Interrupt R Raw interrupt status from the counter Table 25 watchdog interrupt status register |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
