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AS3932 数据表(PDF) 17 Page - ams AG |
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AS3932 数据表(HTML) 17 Page - ams AG |
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17 / 33 page ![]() www.austriamicrosystems.com/AS3932 Revision 1.2 17 - 33 AS3932 Data Sheet - Detailed Description All direct commands are explained below: - clear_wake: clears the wake state of the chip. In case the chip has woken up (WAKE pin is high) the chip is set back to listening mode - reset_RSSI: resets the RSSI measurement. - trim_osc: starts the trimming procedure of the internal RC oscillator (see Figure 22) - clear_false: resets the false wakeup register (R13=00) - preset_default: sets all register in the default mode, as shown in Figure 7 8.3.3.2 Writing of Data to Addressable Registers (WRITE Mode) The SDI is sampled at the falling edge of CLK (as shown in the following diagrams). A CS toggling high-low-high indicates the end of the WRITE command after register has been written. The following example shows a write command. Figure 13. Writing of a Single Byte (falling edge sampling) Figure 14. Writing of Register Data with Auto-incrementing Address 8.3.3.3 Reading of Data from Addressable Registers (READ Mode) Once the address has been sent through SDI, the data can be fed through the SDO pin out to the microcontroller. A CS LOW toggling high-low-high has to be performed after finishing the read mode session, in order to indicate the end of the READ command and prepare the Interface to the next command control Byte. To transfer bytes from consecutive addresses, SDI master has to keep the CS signal high and the SCLK clock has to be active as long as data need to be read. trim_osc 0 00010 clear_false 0 00011 preset_default 0 00100 Table 12. List of Direct Commands COMMAND_MODE B13 B12 B11 B10 B9 B8 CS SCLK SDI 0 0 A5 A4 A3 A2 A1 A0 D5 D 4 D3 D2 D1 D0 D7 D6 X X SCLK raising edge Data is transf ered from µC SCLK falling edge Data is sampled Data is moved t o Address A5-A0 CS falling edge signals end of WRITE Mode Two leading Zeros indicate WRITE Mode CS SCLK SDI 00 A 5 A 4 A 3 A 2 A 1 A 0 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 X X Data is moved t o Address <A5-A0 > + n CS falling edge signals end of WRITE Mode Two leading Zeros indicat e WRI TE Mode D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 1 D 0 Data is moved to Addres s <A5-A0 > + (n- 1) Dat a is mov ed to Addres s <A5-A0> +1 Data is moved t o Address <A5-A0> |
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