AD5175BCPZ-10-R2 datasheet(5/20 Pages) AD

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AD5175

Rev. 0 | Page 5 of 20

Limit at TMIN, TMAX

Parameter

Conditions1

Min

Max

Unit

Description

tRDAC_R-PERF

μs

RDAC register write command execute time (R-Perf mode)

tRDAC_NORMAL

600

RDAC register write command execute time (normal mode)

tMEMORY_READ

μs

Memory readback execute time

tMEMORY_PROGRAM

350

Memory program time

tRESET

600

μs

Reset 50-TP restore time

POWER-UP

Power-on 50-TP restore time

1 Maximum bus capacitance is limited to 400 pF.

2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior

of the part.

3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.

4 Refer to tRDAC_R-PERF and tRDAC_NORMAL for RDAC register write operations.

5 Refer to t

MEMORY_READ

and tMEMORY_PROGRAM for memory commands operations.

6 Maximum time after VDD − VSS is equal to 2.5 V.

Shift Register and Timing Diagrams

DATA BITS

DB9 (MSB)

DB0 (LSB)

CONTROL BITS

Figure 2. Shift Register Content

RESET

t11

t12

t10

SCL

SDA

t13

Figure 3. 2-Wire I2C Timing Diagram

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