AD5175BCPZ-10-R2 datasheet(19/20 Pages) AD

19 / 20 page

AD5175

Rev. 0 | Page 19 of 20

Calculate the Actual End-to-End Resistance

TERMINAL VOLTAGE OPERATING RANGE

The resistance tolerance is stored in the internal memory

during factory testing. The actual end-to-end resistance

can, therefore, be calculated (which is valuable for calibration,

tolerance matching, and precision applications).

The positive VDD and negative VSS power supplies of the AD5175

define the boundary conditions for proper 2-terminal digital

resistor operation. Supply signals present on Terminal A and

Terminal W that exceed VDD or VSS are clamped by the internal

forward-biased diodes (see Figure 30).

The resistance tolerance in percentage is stored in fixed-point

format, using a 16-bit sign magnitude binary. The sign bit(0 =

negative and 1 = positive) and the integer part is located in

Address 0x39, as shown in Table 11. Address 0x3A contains

the fractional part, as shown in Table 12.

VSS

VDD

That is, if the data readback from Address 0x39 is 0000001010

and data from Address 0x3A is 0010110000, then the end-to-end

resistance can be calculated as follows.

For Memory Location 0x39,

DB[9:8]: XX = don’t care

DB[7]: 0 = negative

Figure 30. Maximum Terminal Voltages Set by VDD and VSS

DB[6:0]: 0001010 = 10

The ground pin of the AD5175 is primarily used as a digital

ground reference. To minimize the digital ground bounce, join

the AD5175 ground terminal remotely to the common ground.

The digital input control signals to the AD5175 must be refe-

renced to the device ground pin (GND) and satisfy the logic

level defined in the Specifications section. An internal level

shift circuit ensures that the common-mode voltage range of

the three terminals extends from VSS to VDD, regardless of the

digital input level.

For Memory Location 0x3A,

DB[9:8]: XX = don’t care

DB[7:0]: 10110000 = 176 × 2−8 = 0.6875

Therefore, tolerance = −10.6875% and RWA (1023)= 8.931 kΩ.

EXT_CAP CAPACITOR

A 1 μF capacitor to VSS must be connected to the EXT_CAP pin

(see Figure 29) on power-up and throughout the operation of

the AD5175.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at

Terminal A and Terminal W (see Figure 30), it is important to

power VDD/VSS first before applying any voltage to Terminal A

and Terminal W; otherwise, the diode is forward-biased such

that VDD/VSS are powered unintentionally. The ideal power-up

sequence is VSS, GND, VDD, digital inputs, VA, and VW. The

order of powering VA, VW, and digital inputs is not important

as long as they are powered after VDD/VSS.

AD5175

50-TP

MEMORY

BLOCK

EXT_CAP

1µF

VSS

As soon as VDD is powered, the power-on preset activates,

which first sets the RDAC to midscale and then restores the

last programmed 50-TP value to the RDAC register.

Figure 29. EXT_CAP Hardware Setup

Table 12. End-to-End Resistance Tolerance Bytes

Data Byte1

Memory Map Address

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0x39

Sign

0x3A

2−1

2−2

2−3

2−4

2−5

2−6

2−7

2−8

1 X is don’t care.

AD5175BCPZ-10-R2 数据表(PDF) 19 Page - Analog Devices

AD5175BCPZ-10-R2 数据表(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

数据表下载