AD5175

Rev. 0 | Page 18 of 20

50-TP MEMORY WRITE-ACKNOWLEDGE POLLING

After each write operation to the 50-TP registers, an internal

To determine if the internal write cycle is complete and the

interface polling can be conducted by sending a start condition

face responds with an acknowledge (ACK), the write cycle is

complete and the interface is ready to proceed with further

until it completes.

RESET

The AD5175 can be reset through software by executing

Command 4 (see Table 7) or through hardware on the low

pulse of the RESET pin. The reset command loads the RDAC

register with the contents of the most recently programmed

50-TP memory location. The RDAC register loads with

midscale if no 50-TP memory location has been previously

SHUTDOWN MODE

The AD5175 can be shut down by executing the software

shutdown command, Command 9 (see Table 7), and setting

the LSB to 1. This feature places the RDAC in a zero-power-

consumption state where Terminal A is disconnected from the

wiper terminal. It is possible to execute any command from

Table 7 while the AD5175 is in shutdown mode. The part can

be taken out of shutdown mode by executing Command 9 and

setting the LSB to 0, or by issuing a software or hardware reset.

RDAC ARCHITECTURE

To achieve optimum performance, Analog Devices, Inc., has

patented the RDAC segmentation architecture for all the

digital potentiometers. In particular, the AD5175 employs a

three-stage segmentation approach, as shown in Figure 28.

The AD5175 wiper switch is designed with the transmission

gate CMOS topology.

A

W

10-BIT

ADDRESS

DECODER

Figure 28. Simplified RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance between Terminal W and Terminal A,

the wiper terminal. The 10-bit data in the RDAC latch is decoded

to select one of the 1024 possible wiper settings. As a result, the

general equation for determining the digitally programmed

output resistance between the W terminal and A terminal is

WA

WA

R

D

D

R

×

=

1024

)

(

(1)

where:

D

is the decimal equivalent of the binary code loaded in the

10-bit RDAC register.

is the end-to-end resistance.

In the zero-scale condition, a finite total wiper resistance of

120 Ω is present. Regardless of which setting the part is oper-

ating in, take care to limit the current between the A terminal

to W terminal, and W terminal to B terminal, to the maximum

continuous current of ±6 mA, or the pulse current specified in

Table 3. Otherwise, degradation or possible destruction of the

internal switch contact can occur.