WM8141CFTSLASHV datasheet(14/31 Pages) WOLFSON

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WM8141

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the

difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the

difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,

optionally set via the RLC DAC.

The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the

black level of the input signal towards 0V, producing V2.

The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,

outputting voltage V3.

The ADC BLOCK then converts the analogue signal, V3, to a 12-bit unsigned digital output, D1.

The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.

CALCULATING OUTPUT FOR ANY GIVEN INPUT

The following equations describe the processing of the video and reset level signals through

the WM8141.

INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING

If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the

input video.

=VIN - VRESET ...................................................................

Eqn. 1

If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted

instead.

=VIN - VVRLC ....................................................................

Eqn. 2

If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.

If RLCEXT = 0, VVRLC is the output from the internal RLC DAC.

VVRLC

=(VRLCSTEP

∗ RLCV[3:0]) + VRLCBOT ................................. Eqn. 3

VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.

OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST

The resultant signal V1 is added to the Offset DAC output.

V1 + {260mV

∗ (DAC[7:0]-127.5) } / 27.5 ....................... Eqn. 4

PGA NODE: GAIN ADJUST

The signal is then multiplied by the PGA gain,

∗ 208/(283- PGA[7:0]) .............................................. Eqn. 5

ADC BLOCK: ANALOGUE-DIGITAL CONVERSION

The analogue signal is then converted to a 12-bit unsigned number, with input range configured by

PGAFS[1:0].

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 2047

PGAFS[1:0] = 00 or 01 ......

Eqn. 6

D1[11:0] = INT{ (V3 /VFS)

∗ 4095}

PGAFS[1:0] = 11 ...............

Eqn. 7

D1[11:0] = INT{ (V3 /VFS)

∗ 4095} + 4095

PGAFS[1:0] = 10 ...............

Eqn. 8

where the ADC full-scale range, VFS = 3V at AVDD=5V and VFS = 1.5V at AVDD=3.3V

OUTPUT INVERT BLOCK: POLARITY ADJUST

The polarity of the digital output may be inverted by control bit INVOP.

D2[11:0] = D1[11:0]

(INVOP = 0) ......................

Eqn. 9

D2[11:0] = 4095 – D1[11:0]

(INVOP = 1) ......................

Eqn. 10

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