WM8141CFTSLASHV datasheet(28/31 Pages) WOLFSON

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WM8141

Production Data

WOLFSON MICROELECTRONICS LTD

PD Rev 3.0 October 2000

COLOUR PIXEL-BY-PIXEL

BUFFER

WM8141

INCLUDING

RECOMMENDED

EXTERNAL

COMPONENTS

BUFFER

DATA

CONTROL I/F

CLOCKS

RINP

GINP

BINP

See sensor

datasheet for

details.

SENSOR TIMING

Maximum pixel rate = 1.5Mpixels/second (Mode 5)

Maximum pixel rate = 2Mpixels/second (Mode 1)

SYSTEM

ASIC

Figure 25 Block Diagram of Colour Pixel-By-Pixel Application, AC Coupled

SETTING

NAME

ADDRESS

HEX

BINARY

NOTE

Set-up

000001

0010 0011

EN = 1: Device enabled;

CDS = 1: CDS enabled;

MONO = 0: Colour operation;

SELPD = 0: No selective power down;

PGAFS[1:0] = 10: ADC range optimised for

negative going video;

MODE4 = 0: Not required for colour.

Set-up

000010

0010 0000

MUXOP[1:0] = 00: 12-bit parallel output;

INVOP = 0: Output data not inverted;

VRLCEXT = 0: RLCDAC required to provide

reset level clamp voltage since sensor is

AC coupled;

RLCDACRNG = 1: RLCDAC range is 0V

to VRT;

DEL[1:0] = 00: Default latency

Set-up

000011

XX01 1111

RLCV[3:0] = 1111: RLCDAC full scale voltage;

CDSREF[1:0] = 01: Default reset sample

position;

CHAN[1:0] = XX: Colour mode so not

required.

Set-up

000101

0000 0000

Line-by-Line mode not used so this register is

not required.

Set-up

001000

0000 0000

Only used if programmable VSMP circuit is

required.

Set-up

001001

0000 0000

All channels enabled.

Table 9

Typical Control Register Settings for Figure 25 (CDS, Negative-Going CCD

Video Signal, MCLK:VSMP = 6:1/8:1)

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