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WM8721 数据表(PDF) 7 Page - Wolfson Microelectronics plc

部件名 WM8721
功能描述  Internet Audio DAC with Integrated Headphone Driver
PDF  34 Pages
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制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8721 数据表(HTML) 7 Page - Wolfson Microelectronics plc

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WM8721
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WOLFSON MICROELECTRONICS LTD
PP Rev 1.3 November 2000
7
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
(Output)
DACLRC
(Output)
DACDAT
t
DLT
t
DHT
t
DL
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
DACLRC propagation delay
from BCLK falling edge
tDL
010
ns
DACDAT setup time to
BCLCK rising edge
tDST
10
ns
DACDAT hold time from
BCLK rising edge
tDHT
10
ns
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
DACLRC
t
BCH
t
BCL
t
BCY
DACDAT
t
LRSU
t
DS
t
LRH
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25
oC, slave mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
DACLRC set-up time to
BCLK rising edge
tLRSU
10
ns
DACLRC hold time from
BCLK rising edge
tLRH
10
ns
DACDAT set-up time to
BCLK rising edge
tDS
10
ns
DACDAT hold time from
BCLK rising edge
tDH
10
ns



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