WM8721

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WOLFSON MICROELECTRONICS LTD

PP Rev 1.3 November 2000

24

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE

To prevent any communication problems from arising across the Digital Audio Interface is disabled

(tristate) at power on. Once the Audio Interface and the Sampling Control has been programmed it is

activated by setting the ACTIVE bit under Software Control.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

Active Control

0

ACTIVE

0

Activate Interface

1 = Active

0 = Inactive

Table 15 Activating DSP and Digital Audio Interface

It is recommended that between changing any content of Digital Audio Interface or Sampling Control

Register that the active bit is reset then set.

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using either a 3-wire or 2-wire MPU interface.

Selection of interface format is achieved by setting the state of the MODE pin.

In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and

CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is

used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two

addresses.

Unused bits in the Register Map should be set to ‘0’ unless specified otherwise (see Powerdown

section).

SELECTION OF SERIAL CONTROL MODE

The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved

by setting the state of the MODE pin.

MODE

INTERFACE

FORMAT

02 wire

13 wire

Table 16 Control Interface Mode Selection

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

The WM8721 can be controlled using a 3-wire serial interface. SDIN is used for the program data,

SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire

interface protocol is shown in Figure 18.

CSB

SCLK

SDIN

B15

B6

B7

B8

B9

B10

B11

B12

B13

B14

B1

B2

B3

B4

B5

B0

Figure 18 3-Wire Serial Interface

Notes:

1.

B[15:9] are Control Address Bits

2.

B[8:0] are Control Data Bits