数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

WM8721 数据表(PDF) 16 Page - Wolfson Microelectronics plc

部件名 WM8721
功能描述  Internet Audio DAC with Integrated Headphone Driver
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  WOLFSON [Wolfson Microelectronics plc]
网页  http://www.wolfsonmicro.com
标志 WOLFSON - Wolfson Microelectronics plc

WM8721 数据表(HTML) 16 Page - Wolfson Microelectronics plc

Back Button WM8721 Datasheet HTML 12Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 13Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 14Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 15Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 16Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 17Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 18Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 19Page - Wolfson Microelectronics plc WM8721 Datasheet HTML 20Page - Wolfson Microelectronics plc Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 34 page
background image
WM8721
Product Preview
WOLFSON MICROELECTRONICS LTD
PP Rev 1.3 November 2000
16
The digital audio interface receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK high to low transition.
DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the
device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8721. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a
DACLRC transition.
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1/fs
n
3
2
1
n-2
n-1
LSB
MSB
n
3
2
1
n-2
n-1
LSB
MSB
Figure 12 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK
transition.
LEFT CHANNEL
RIGHT CHANNEL
DACLRC
BCLK
DACDAT
1/fs
n
3
2
1
n-2
n-1
LSB
MSB
n
3
2
1
n-2
n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 13 I2S Mode



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com