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WM8728 数据表(PDF) 7 Page - Wolfson Microelectronics plc |
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WM8728 数据表(HTML) 7 Page - Wolfson Microelectronics plc |
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7 / 28 page ![]() WM8728 Product Preview WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 7 DSD AUDIO MONOPHASE INTERFACE MCLK t BCH t BCL t BCY DIN/LRCIN t DS t DH Figure 3 Normal DSD timing requirements Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information MCLK cycle time tBCY 344 ns MCLK pulse width high tBCH 160 ns MCLK pulse width low tBCL 160 ns DIN/LRCIN set-up time to MCLK rising edge tDS 10 ns DIN/LRCIN hold time from MCLK rising edge tDH 10 ns |
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