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WM8728 数据表(PDF) 9 Page - Wolfson Microelectronics plc |
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WM8728 数据表(HTML) 9 Page - Wolfson Microelectronics plc |
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9 / 28 page ![]() WM8728 Product Preview WOLFSON MICROELECTRONICS LTD PP Rev 1.2 April 2001 9 MPU 3-WIRE INTERFACE TIMING LATI2S SCKDSD SDIDEM t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS CSBIWL t CSSH t CSSU Figure 5 Program Register Input Timing - 3-Wire Serial Control Mode Test Conditions AVDD, DVDD = 5V, AGND = 0V, DGND = 0V, TA = +25 oC, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCKDSD rising edge to LATI2S rising edge tSCS 40 ns SCKDSD pulse cycle time tSCY 80 ns SCKDSD pulse width low tSCL 20 ns SCKDSD pulse width high tSCH 20 ns SDIDEM to SCKDSD set-up time tDSU 20 ns SCKDSD to SDIDEM hold time tDHO 20 ns LATI2S pulse width low tCSL 20 ns LATI2S pulse width high tCSH 20 ns LATI2S rising to SCKDSD rising tCSS 20 ns CSBIWL to LATI2S set-up time tCSSU 20 ns LATI2S to CSBIWL hold time tCSSH 20 ns |
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