WM8728

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WOLFSON MICROELECTRONICS LTD

PP Rev 1.2 April 2001

13

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN

transition. LRCIN is high during the left data word and low during the right data word.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 8 Right Justified Mode Timing Diagram

I

In I

transition. LRCIN is low during the left data word and high during the right data word.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

Figure 9 I

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN rising edge following the one that

detects a low to high transition on LRCIN. No BCKIN edges are allowed between the data words.

The word order is DIN left, DIN right.

LRCIN

BCKIN

DIN

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n

2

1

n-1

LSB

MSB

n

2

1

n-1

RIGHT CHANNEL

NO VALID DATA

1 BCKIN

1 BCKIN

Figure 10 DSP Early Mode Timing Diagram