ADL5902ACPZ-R7 datasheet(18/28 Pages) AD

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ADL5902

Rev. 0 | Page 18 of 28

stability of the RF measurement system. Typically, the

temperature compensation circuit responds only to voltages

between 0 and VS/2, or about 2.5 V when VS = 5 V.

Figure 41 in the Power-Down Interface section shows a simpli-

fied schematic representation of the TADJ/PWDN interface.

POWER-DOWN INTERFACE

The quiescent and disabled currents for the ADL5902 at 25°C

are approximately 73 mA and 300 µA, respectively. The dual

function TADJ/PWDN pin is connected to the temperature

compensation circuit as well as the power-down circuit.

Typically, the temperature compensation circuit responds only

to voltages between 0 and VS/2, or about 2.5 V when VS = 5 V.

When the voltage on this pin is greater than VS − 0.1 V, the

device is fully powered down. Figure 32 shows this charac-

teristic as a function of VPWDN. Note that, because of the design

of this section of the ADL5902, as VPWDN passes through a

narrow range at ~4.5 V (or ~VS − 0.5 V), the TADJ/PWDN pin

sinks approximately 500 µA. The source used to disable the

ADL5902 must have a sufficiently high current capability for this

reason. Figure 33 shows the typical response times for various

RF input levels. The output reaches within 0.1 dB of its steady-

state value in approximately 5 µs; however, the reference voltage is

available to full accuracy in a much shorter time. This wake-up

response varies depending on the input coupling and CLPF.

TADJ/

PWDN

COMM

VPOS

200

Ω

200

Ω

VREF

INTERCEPT

TEMPERATURE

COMPENSATION

200

Ω

POWER-UP

CIRCUIT

SHUTDOWN

CIRCUIT

ESD

Figure 41. TADJ/PWDN Interface Simplified Schematic

VSET INTERFACE

The VSET interface has a high input impedance of 72 kΩ. The

voltage at VSET is converted to an internal current used to set

the internal VGA gain. The VGA attenuation control is approx-

imately 19 dB/V.

ACOM

2.5k

Ω

18k

Ω

VSET

GAIN ADJUST

54k

Ω

Figure 42. VSET Interface Simplified Schematic

OUTPUT INTERFACE

The ADL5902 incorporates rail-to-rail output drivers with pull-

up and pull-down capabilities. The closed-loop, − 3dB band-

width from the input of the output amplifier to the output with

no load is approximately 58 MHz with a single-pole roll off of

approximately −20 dB/decade. The output noise is approxi-

mately 25 nV/√Hz at 100 kHz. The VOUT pin can source and

sink up to 10 mA. There is also an internal load from VOUT

to COMM of 2500 Ω.

VOUT

CLPF

Ω

500

Ω

2pF

ESD

VPOS

COMM

Figure 43. VOUT Interface Simplified Schematic

VTGT INTERFACE

The target voltage can be set with an external source or by

connecting the VREF pin (nominally 2.3 V) to the VTGT pin

through a resistive voltage divider. With 0.8 V on the VTGT pin,

the rms voltage that must be provided by the VGA to balance the

AGC feedback loop is 0.8 V × 0.05 = 40 mV rms. Most of the

characterization information in this data sheet was collected at

VTGT = 0.8 V. Voltages higher and lower than this can be used;

however, doing so increases or decreases the gain at the internal

squaring cell, which results in a corresponding increase or

decrease in intercept. This, in turn, affects the sensitivity and the

usable measurement range, in addition to the sensitivity to

different carrier modulation schemes. As VTGT decreases, the

squaring circuits produce more noise; this becomes noticeable

in the output response at low input signal amplitudes. As VTGT

increases, measurement error due to modulation increases and

temperature drift tends to decrease. The chosen VTGT value of

0.8 V represents a compromise between these characteristics.

VTGT

50k

Ω

50k

Ω

10k

Ω

ESD

VPOS

COMM

g × X2

ITGT

Figure 44. VTGT Interface

BASIS FOR ERROR CALCULATIONS

The slope and intercept used in the error plots are calculated using

the coefficients of a linear regression performed on data collected

in its central operating range. The error plots in the Typical

Performance Characteristics section are shown in two formats:

error from the ideal line and error with respect to the 25°C

output voltage. The error from the ideal line is the decibel

difference in VOUT from the ideal straight-line fit of VOUT

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