ADL5902ACPZ-R7 datasheet(20/28 Pages) AD

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ADL5902

Rev. 0 | Page 20 of 28

SETTING VTADJ

As discussed in the Theory of Operation section, the output

temperature drift must be compensated by applying a voltage to

the TADJ pin. The compensating voltage varies with frequency.

The voltage for the TADJ pin can be easily derived from a resistor

divider connected to the VREF pin. Table 5 shows the recom-

mended VTADJ for operation from −40°C to +85°C, along with

resistor divider values. Resistor values are chosen so that they

neither pull too much current from VREF (VREF short-circuit

current is 4 mA) nor are so large that the TADJ pin’s bias current of

3 µA affects the resulting voltage at the TADJ pin.

Table 5. Recommended VTADJ for Selected Frequencies

Frequency

VTADJ (V)

R9 (Ω)

R12 (Ω)

100 MHz

0.5

1430

402

700 MHz to 2.14 GHz

0.4

1430

301

2.6 GHz

0.45

1430

348

3.5 GHz

0.5

1430

402

5.8 GHz

0.95

1430

1007

SETTING VTGT

As discussed in the Theory of Operation section, setting the

voltage on VTGT to 0.8 V represents a compromise between

achieving excellent rms compliance and maximizing dynamic

range. The voltage on VTGT can be derived from the VREF pin

using a resistor divider as shown Figure 45. Like the resistors

chosen to set the VTADJ voltage, the resistors setting VTGT should

have reasonable values that do not pull too much current from

VREF or cause bias current errors. Also, attention should be

paid to the combined current that VREF must deliver to

generate the VTADJ and VTGT voltages. This current should be

kept well below the VREF short-circuit current of 4 mA.

CHOOSING A VALUE FOR CLPF

CLPF provides the averaging function for the internal rms

computation. Using the minimum value for CLPF allows the

quickest response time to a pulsed waveform but leaves

significant output noise on the output voltage signal. By the

same token, a large filter cap reduces output noise but at the

expense of response time.

For non response-time critical applications, a relatively large

capacitor can be placed on the CLPF pin. In Figure 45, a value

of 10 µF is used. For most signal modulation schemes, this value

ensures excellent rms measurement compliance and low

residual output noise. There is no maximum capacitance limit

for CLPF.

Figure 46 shows how output noise varies with CLPF when the

ADL5902 is driven by a single-carrier W-CDMA signal (Test

Model TM1-64, peak envelope power = 10.56 dB, bandwidth =

3.84 MHz). With a 10 µF capacitor on CLPF, there is residual

noise on VOUT of 4.4 mV p-p, which is less than 0.1 dB error

(assuming a slope of approximately 53 mV/dB).

100

10k

100k

100

150

200

250

300

100

1000

CLPF (nF)

OUTPUT NOISE (mV p-p)

10% TO 90% RISE TIME (µs)

90% TO 10% FALL TIME (µs)

Figure 46. Output Noise, Rise and Fall Times vs. CLPF Capacitance, Single-

Carrier W-CDMA (TM1-64) at 2.14 GHz with PIN = 0 dBm

Figure 46 also shows how the response time is affected by the

value of CLPF. To measure this, a RF burst at 2.14 GHz at

−10 dBm was applied to the ADL5902. The 10% to 90% rise

time and 90% to 10% fall time were then measured. It is notable

that the fall time is much longer than the rise time. This can

also be seen in the response time plots, Figure 22, Figure 23,

Figure 25, and Figure 26.

In applications where the response time is critical, a different

approach to signal filtering can be taken. This is shown in

Figure 47. The capacitor on the CLPF pin is set to the minimum

value that ensures that a valid rms computation has been

performed. The job of noise removal is then handed off to an

RC filter on the VOUT pin. This approach ensures that there is

enough averaging to ensure good rms compliance and does not

burden the rms computation loop with extra filtering that will

significantly slow down the response time. By finishing the

filtering process using an RC filter after VOUT, faster fall times

can be achieved with an equivalent amount of output noise. It

should be noted that the RC filter can also be implemented in

the digital domain after the analog-to-digital converter.

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