ADL5902

Rev. 0 | Page 25 of 28

EVALUATION BOARD SCHEMATICS AND ARTWORK

TEMP

VPOS

C9

0.1µF

C8

OPEN

8

7

6

5

VSET

VOUT

VOUTP

C10

0.1µF

C6

OPEN

VPOSC

13

14

15

16

C5

100pF

VPOS2

R10

1.87k

Ω

R11

1k

Ω

C7

0.1µF

12

11

10

9

1

2

3

GND

4

C4

100pF

C12

0.1µF

C11

OPEN

C13

0.1µF

PADDLE

AGND

NC

INHI

INLO

NC

TEMP

VSET

VOUT

CLPF

ADL5902

DUT1

VPOS1

TC2_PWDN

VREF

R16

0

Ω

R5

0

Ω

R2

OPEN

R14

0

Ω

R8

0

Ω

R13

OPEN

R1

0

Ω

R6

0

Ω

R9

1430

Ω

R12

301

Ω

R3

60.4

Ω

IN

R7

0

Ω

R15

0

Ω

VREF

VTGT

GND

Figure 54. Evaluation Board Schematic

Table 8. Evaluation Board Configuration Options

Component

Function/Notes

Default Value

C6, C10, C11,

C12, R3

RF input. The ADL5902 is generally driven single-ended. When driving INHI, populate C10 and C12

with an appropriate capacitor value for the frequency of operation and leave C6 and C11 open.

When driving INLO, populate C6 and C11 with an appropriate capacitor value for the frequency of

operation and leave C10 and C12 open. R3 is the input termination resistor and is chosen to give a

50 Ω input impedance over a broad frequency range.

C6 = open,

C10 = C12 = 0.1 µF,

C11 = open,

R3 = 60.4 Ω

R7, R8, R10,

R11

VTGT interface. R10 and R11 are set up to provide 0.8 V to VTGT derived from VREF. If R10 and R11

are removed, an external voltage can be applied. Alternatively, R7 and R11 can be used to form a

voltage divider for an external reference.

R7 = R8 = 0 Ω,

R10 = 1.87 kΩ,

R11 = 1k Ω

C4, C5, C7,

C13, R14, R16

Power supply decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor

placed close to the ADL5902, a 0 Ω series resistor, and a 0.1 μF capacitor placed close to the power

supply input pin.

C4 = C5 = 100 pF,

C7 = C13 = 0.1 µF,

R14 = R16 = 0 Ω

R1, R2, R6,

R13, R15

Output interface. In measurement mode, a portion of the voltage at the VOUT pin is fed back to

the VSET pin via R6. Using the voltage divider created by R2 and R6, the magnitude of the slope of

must be open and R13 must have a 0 Ω resistor. In this mode, the ADL5902 can control the gain of

an external component. A setpoint voltage is applied to the VSET pin, the value of which

corresponds to the desired RF input signal level applied to the ADL5902.

R1 = R6 = R15 = 0 Ω,

R2 = R13 = open

C8, C9, R5

affect the response time of the ADL5902.

C8 = open,

C9 = 0.1 µF,

R5 = 0 Ω,

R9, R12

TADJ/PWDN. The TADJ/PWDN pin controls the amount of nonlinear intercept temperature

compensation and/or shuts down the device. The evaluation board is configured with TADJ

connected to VREF through a resistor divider (R9, R12).

R9 = 1430 Ω

R12 = 301 Ω

Paddle

The paddle should be tied to both a thermal ground and an electrical ground.