Low Noise, Matched

Dual Monolithic Transistor

Preliminary Technical Data

MAT12

Rev. PrA

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FEATURES

PIN CONFIGURATION

Very Low Voltage Noise: 1nV/

√Hz max @ 100Hz

Low Offset Voltage Drift: 0.1 μV/ºC max

High Gain Bandwidth Product: 200MHz

Note: Substrate is connected to case on TO-78 package. Substrate is

normally connected to the most negative circuit potential, but can

be floated

GENERAL DESCRIPTION

The design of the MAT12 series of NPN dual monolithic transistors is optimized for very low noise, low drift and

which is maintained over a wide range of collector current. Device performance is specified over the full

temperature range as well as at 25

°C.

Input protection diodes are provided across the emitter-base junctions to prevent degradation of the device

characteristics due to reverse-biased emitter current. The substrate is clamped to the most negative emitter by the

parasitic isolation junction created by the protection diodes. This results in complete isolation between the

transistors.

The MAT12 is ideal for applications where low noise is a priority. The MAT12 can be used as an input

stage to make an amplifier with noise voltage of less than 1.0 nV/

√Hz at 100 Hz. Other applications, such as

log/antilog circuits, may use the excellent logging conformity of the MAT12. Typical bulk resistance is only 0.3

Ω to 0.4 Ω. The MAT12 electrical characteristics approach those of an ideal transistor when operated over a

collector current range of 1µA to 10 mA.