PCF8563 datasheet(18/32 Pages) NXP

18 / 32 page

PCF8563_6

Product data sheet

Rev. 06 — 21 February 2008

18 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

[1]

For reliable oscillator start-up at power-up: VDD(min)power-up =VDD(min) + 0.3 V.

[2]

Timer source clock = 1

⁄

60 Hz, level of pins SCL and SDA is VDD or VSS.

[3]

Tested on sample basis.

IDD

supply current

interface inactive (fSCL = 0 Hz); CLKOUT

enabled at 32 kHz; Tamb =25 °C; see Figure 18

[2]

VDD = 5.0 V

825

1600

VDD = 3.0 V

550

1000

VDD = 2.0 V

425

800

interface inactive (fSCL = 0 Hz); CLKOUT

enabled at 32 kHz; Tamb = −40 °C to +85 °C;

see Figure 18

[2]

VDD = 5.0 V

950

1700

VDD = 3.0 V

650

1100

VDD = 2.0 V

500

900

Inputs

VIL

LOW-level input

voltage

VSS

0.3VDD

VIH

HIGH-level input

voltage

0.7VDD

-VDD

ILI

input leakage

current

VI =VDD or VSS

−10

µA

input

capacitance

[3] --7

Outputs

IOL

LOW-level

output current

VOL = 0.4 V; VDD =5V

on pin SDA

−3

--mA

on pin INT

−1

--mA

on pin CLKOUT

−1

--mA

IOH

HIGH-level

output current

on pin CLKOUT; VOH = 4.6 V; VDD =5V

ILO

output leakage

current

VO =VDD or VSS

−10

µA

Voltage detector

Vlow

low voltage

Tamb =25 °C; sets bit VL; see Figure 7

0.9

1.0

Table 27.

Static characteristics …continued

VDD = 1.8 V to 5.5 V; VSS =0V; Tamb = −40 °C to +85 °C; fosc = 32.768 kHz; quartz Rs =40kΩ; CL = 8 pF; unless otherwise

speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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