PCF8563_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 21 February 2008

11 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

7.7 EXT_CLK test mode

A Test mode is available which allows for on-board testing. In such a mode it is possible to

set up test conditions and control the operation of the RTC.

The Test mode is entered by setting bit TEST1 in control_status_1 register. Then

pin CLKOUT becomes an input. The Test mode replaces the internal 64 Hz signal with the

signal applied to pin CLKOUT. Every 64 positive edges applied to pin CLKOUT will then

generate an increment of one second.

The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a

minimum period of 1000 ns. The internal 64 Hz clock, now sourced from CLKOUT, is

into a known state by using bit STOP. When bit STOP is set, the pre-scaler is reset to 0

(STOP must be cleared before the pre-scaler can operate again).

From a STOP condition, the first 1 second increment will take place after 32 positive

edges on CLKOUT. Thereafter, every 64 positive edges will cause a one-second

increment.

Remark: Entry into EXT_CLK test mode is not synchronized to the internal 64 Hz clock.

When entering the Test mode, no assumption as to the state of the pre-scaler can be

made.

Table 22.

Timer_control - Timer control register (address 0Eh) bit description

Bit

Symbol

Value

Description

7

TE

0

timer is disabled

1

timer is enabled

6 to 2

x

not relevant

1 to 0

TD[1:0]

see Table 23

timer source clock frequency select; these bits

determine the source clock for the countdown

timer; when not in use, TD[1:0] should be set

⁄

Table 23.

TD1 and TD0: Timer frequency selection

TD1

TD0

TIMER Source clock frequency

0

0

4096 Hz

0

1

64 Hz

10

1 Hz

11

1

Table 24.

Timer - Timer value register (address 0Fh) bit description

Bit

Symbol

Value

Description

7 to 0

TIMER

00h to FFh

countdown value = n;

CountdownPeriod

n

SourceClockFrequency

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