PCF8563_6

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 06 — 21 February 2008

14 of 32

NXP Semiconductors

PCF8563

Real-time clock/calendar

8.3 System configuration

A device generating a message is a transmitter, a device receiving a message is a

receiver. The device that controls the message is the master and the devices which are

controlled by the master are the slaves (see Figure 11).

8.4 Acknowledge

The number of data bytes transferred between the START and STOP conditions from

transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge

bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during

which time the master generates an extra acknowledge-related clock pulse. A slave

receiver which is addressed must generate an acknowledge after the reception of each

byte. Also a master receiver must generate an acknowledge after the reception of each

byte that has been clocked out of the slave transmitter (see Figure 12).

The device that acknowledges must pull down the SDA line during the acknowledge clock

pulse, so that the SDA line is stable LOW during the HIGH period of the

acknowledge-related clock pulse (set-up and hold times must be taken into

consideration). A master receiver must signal an end of data to the transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

event the transmitter must leave the data line HIGH to enable the master to generate a

STOP condition.

Fig 10. Definition of start and stop conditions

mbc622

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

Fig 11. System configuration

mba605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

SDA

SCL