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PCF8564AU/5GE/1 数据表(PDF) 16 Page - NXP Semiconductors |
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PCF8564AU/5GE/1 数据表(HTML) 16 Page - NXP Semiconductors |
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16 / 44 page ![]() PCF8564A_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 1 — 8 October 2009 16 of 44 NXP Semiconductors PCF8564A Real time clock and calendar [1] Default value. 8.8 Timer function The 8-bit countdown timer at address 0Fh is controlled by the timer control register at address 0Eh. The timer control register determines one of 4 source clock frequencies for the timer (4.096 kHz, 64 Hz, 1 Hz, or 1 ⁄ 60 Hz) and enables or disables the timer. The timer counts down from a software-loaded 8-bit binary value. At the end of every countdown, the timer sets the TF (Timer Flag) to logic 1. The TF may only be cleared using the interface. The generation of interrupts from the timer function is controlled via bit TIE. If bit TIE is enabled the INT pin follows the condition of bit TF. The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of the timer flag TF. TI_TP is used for this mode control. When reading the timer, the current countdown value is returned. 8.8.1 Register Timer_ctrl [1] Default value. [2] These bits determine the source clock for the countdown timer; when not in use, TD[1:0] should be set to 1 ⁄60 Hz for power saving. Table 22. CLKOUT_ctrl - CLKOUT control register (address 0Dh) bit description Bit Symbol Value Description 7 FE 0 the CLKOUT output is inhibited and CLKOUT output is set to logic 0 1[1] the CLKOUT output is activated 6 to 2 - - unused 1 to 0 FD[1:0] frequency output at pin CLKOUT 00[1] 32.768 kHz 01 1.024 kHz 10 32 Hz 11 1 Hz Table 23. Timer_ctrl - timer control register (address 0Eh) bit description Bit Symbol Value Description 7TE 0[1] timer is disabled 1 timer is enabled 6 to 2 - - unused 1 to 0 TD[1:0] timer source clock frequency select[2] 00 4.096 kHz 01 64 Hz 10 1 Hz 11[2] 1 ⁄60 Hz |
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