ADRF6510ACPZ-R7 datasheet(15/28 Pages) AD

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ADRF6510

Rev. 0 | Page 15 of 28

4.0

The corner frequency of the filters is defined by RC products,

which can vary by ±30% in a typical process. Therefore, all the

parts are factory calibrated for corner frequency, resulting in

a residual ±10% corner frequency variation over the −40°C to

+85°C temperature range. Although absolute accuracy requires

calibration, the matching of RC products between the pair of

channels is better than 1% by observing careful design and

layout practices. Calibration and excellent matching ensure

that the magnitude and group delay responses of both channels

track together, a critical requirement for digital IQ-based

communication systems.

VARIABLE GAIN AMPLIFIERS (VGAs)

The VGAs are implemented using the Analog Devices, Inc.,

patented X-AMP® architecture, consisting of a tapped 50 dB

attenuator followed by a fixed-gain amplifier. The X-AMP archi-

tecture generates a linear-in-dB monotonic gain response with

low ripple. The gain is controlled through the high impedance

GAIN pin with an accurate slope of 30 mV/dB. The gain response

shown in Figure 44 shows the GAIN pin voltage range and the

absence of gain foldback at high VGAIN.

–10

0.3

–0.3

VGAIN (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–0.2

–0.1

0.1

0.2

30mV/dB

Figure 44. Linear-in-dB Gain Control Response of the X-Amp VGA

Showing Consistent Slope and Low Error

OUTPUT BUFFERS/ADC DRIVERS

The low impedance (20 Ω) output buffers of the ADRF6510 are

designed to drive either ADC inputs or subsequent amplifier stages.

They are capable of delivering up to 4 V p-p composite two-tone

signals into 500 Ω differential loads with >60 dBc IM3. The

output common-mode voltage defaults to VPS/2, but it can be

adjusted from 1.5 V to 3.0 V without loss of drive capability by

presenting the VOCM pin with the desired common-mode

voltage. The high input impedance of VOCM allows the ADC

reference output to be connected directly. Even though the

signal path is fully dc-coupled and the dc offset compensation

loop can remove undesired dc offsets (see the DC Offset

Compensation Loop section), the output buffers can be ac-

coupled to the next stage by properly selecting the coupling

capacitors according to the load impedance.

DC OFFSET COMPENSATION LOOP

In many signal processing applications, no information is

carried in the dc level. In fact, dc voltages and other low

frequency disturbances can often dominate the intended signal

and consume precious dynamic range in the analog path and

bits in the data converters. These dc voltages can be present

with the desired input signal or can be generated inside the

signal path by inherent dc offsets or other unintended signal-

dependent processes such as self-mixing or rectification.

Because the ADRF6510 is fully dc-coupled, it may be necessary

to remove these offsets to realize the maximum signal-to-noise

ratio (SNR). This can be achieved with ac-coupling capacitors

at the input and output pins, but that would require large values

because the impedances are fairly low, and high-pass corners

may need to be <10 Hz in some cases. To address the issue of dc

offsets, the ADRF6510 provides an offset correction loop that

nulls the output differential dc level as shown in Figure 45. If

the correction loop is not required, it can be disabled through

the OFDS pin.

GAIN

FROM

FILTERS

COFS

OFSx

OFDS

50dB

VGA

OUTPUT ADC

DRIVER

BASEBAND

OUTPUT

Figure 45. Offset Compensation Loop Operates Around the VGA

and Output Buffer

The offset control loop creates a high-pass corner, fHP, that

is superimposed on the normal Butterworth filter response.

Typically, fHP is many orders of magnitude lower than the lower

programmed filter bandwidth so that there is no interaction

between them. Setting fHP is accomplished with capacitors,

COFS, from the OFS1 and OFS2 pins to ground. Because the

correction loop works around the VGA section, fHP is also

dependent on the gain of the VGA. In general, the expression

for fHP is given by

fHP (Hz) = 1.2 × (Gain/COFS)

where:

Gain is expressed in linear terms, not in decibels (dB).

COFS is expressed in microfarads (μF).

Note that fHP increases in proportion to the gain. For this

reason, COFS should be chosen at the highest operating gain

to guarantee that fHP is always below the maximum limit

required by the system.

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